On-chip Interconnection Networks Research Articles

A Generic Optical Router Design for Photonic Network-on-Chips

Photonic network-on-chip (NoC) architectures are emerging as a new paradigm to interconnect a large number of processing cores at chip level, meeting the pressing demand for extremely high bandwidth and low power consumption. Optical routers, which are typically composed of silicon waveguides and optical switches, play a key role in an on-chip photonic interconnection network. In this paper, we propose a micro-ring-resonator (MRR)-based, scalable, and non-blocking passive optical router design, namely the generic wavelength-routed optical router (GWOR). We first introduce the four 4 × 4 GWOR router structures and then show how to construct GWORs of larger sizes by using the proposed 4 × 4 GWORs as the primitive building blocks. The number of MRRs used in the proposed GWOR is the least among the existing passive router designs for the same network size. In addition, we show that the power loss experienced on GWORs is lower than other comparative designs. Furthermore, to improve the bandwidth and fault tolerance capability of the GWORs, the redundant GWOR (RGWOR) structure is presented. RGWOR can provide multiple routing paths between each pair of input-output ports by cascading different types of GWORs.

A Two-Dimensional Low-Diameter Scalable On-Chip Network for Interconnecting Thousands of Cores

This paper introduces the Spidergon-Donut (SD) on-chip interconnection network for interconnecting 1,000 cores in future MPSoCs and CMPs. Unlike the Spidergon network, the SD network which extends the Spidergon network into the second dimension, significantly reduces the network diameter, well below the popular 2D Mesh and Torus networks for one extra node degree and roughly 25 percent more links. A detailed construction of the SD network and a method to reshuffle the SD network's nodes for layout onto the 2D plane, and simple one-to-one and broadcast routing algorithms for the SD network are presented. The various configurations of the SD network are analyzed and compared including detailed area and delay studies. To interconnect a thousand cores, the paper concludes that a hybrid version of the SD network with smaller SD instances interconnected by a crossbar is a feasible low-diameter network topology for interconnecting the cores of a thousand core system.

A non-blocking switching network and routing algorithms for on-chip networks

The on-chip interconnection network (OCIN) and routing algorithms play an important role in the performance of a chip multiprocessor (CMP). As the number of cores in CMP increases, the OCIN also should scale efficiently to make use of the increasing processing capacity. An ideal OCIN should provide maximum throughput and minimum latency. We propose using a 2-dilated flattened butterfly (2DFB) instead of a mesh as a high- radix OCIN because of its non-blocking property and reduced diameter. We also present ALDFB, an adaptive load balanced routing scheme for 2DFB networks. We evaluate the performance of the 2DFB OCIN with ALDFB routing using synthetic traffic patterns and compare it with a mesh network having the samebisection bandwidth, which uses adaptive minimal routing scheme. We also compare the performance of ALDFB with two other most popular adaptive routing schemes. We observe that 2DFB with ALDFB provides significant improvement in terms of throughput and latency.

Networks‐on‐Chip: Architectures, Design Methodologies, and Case Studies

As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a Multi-Processor System-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructures. Networks-on-Chip (NoC) has been proposed in recent years as a promising solution of on-chip interconnection network to provide better scalability, performance, and modularity for current and future MP-SoC architectures. The paper entitled “Networks on chips: structure and design methodologies” introduces several NoC architectures and discusses the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Then, a novel Bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is presented, which can break the performance bottleneck caused by bandwidth restriction in conventional NoCs. Since buffers in on-chip networks constitute a significant proportion of the power consumption and the area of interconnects, reducing the buffer size is an important problem. The paper entitled “A buffer sizing algorithm for network on chips with multiple voltage-frequency islands” describes a two-phase algorithm to size the switch buffers in NoC in considering the support of multiple-frequency islands. The paper entitled “Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks” depicts the design of an energy-efficient and reliable channel for on-chip interconnection networks (OCINs) using a self-calibrated voltage scaling technique with self-corrected green (SCG) coding scheme. Among the NoC components, links that connect the NoC routers are the most power-hungry components. The paper entitled “Intelligent on/off dynamic linkmanagement for onchip networks” presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status, where links are turned off and on via the use of a small and scalable neural network. Monitoring and diagnostic systems are required in modern NoC implementations to assure high performance and reliability. In the paper entitled “Status data and communication aspects in dynamically clustered network-onchip monitoring,” the design of a dynamically clustered NoC monitoring structure for traffic and fault monitoring is illustrated. Since biological organisms have better adaptability than computer systems in dealing with environmental changes or noise. A case study on the design of an evolvable neuromolecular hardware motivated from some biological evidence, which integrates interand intra-neuronal information processing, is depicted in the paper entitled “A hardware design of neuromolecular network with enhanced resolvability: a bio-inspired approach.”

Performance analysis of minimal path fault tolerant routing in NoC

Occurrence of faults in Network on Chip (NoC) is inevitable as the feature size is con- tinuously decreasing and processing elements are increasing in numbers. Faults can be revocable if it is transient. Transient fault may occur inside router, or in the core or in communication wires. Examples of transient faults are overflow of buffers in router, clock skew, cross talk, etc.. Revocation of transient faults can be done by retransmission of faulty packets using oblivious or adaptive routing algorithms. Irrevocable faults causes non-functionality of segment and mainly occurs during fabrication process. NoC reliability increases with the efficient routing algorithms, which can handle the maximum faults without deadlock in network. As transient faults are temporary and can be easily revoked using re- transmission of packet, permanent faults require efficient routing to route the packet by bypassing the nonfunctional segments. Thus, our focus is on the analysis of adaptive minimal path fault tolerant routing to handle the permanent faults. Comparative analysis between partial adaptive fault tolerance routing West-First, North-Last, Negative-First, Odd Even, and Minimal path Fault Tolerant routing (MinFT) algorithms with the nodes and links failure is performed using NoC Interconnect RoutinG and Application Modeling simulator (NIRGAM) for the 2D Mesh topology. Result suggests that MinFT ensures data transmission under worst conditions as compared to other adaptive routing algorithms .

Self‐Calibrated Energy‐Efficient and Reliable Channels for On‐Chip Interconnection Networks

Energy‐efficient and reliable channels are provided for on‐chip interconnection networks (OCINs) using a self‐calibrated voltage scaling technique with self‐corrected green (SCG) coding scheme. This self‐calibrated low‐power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self‐calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects

With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead.

Design and evaluation of low latency interconnection networks for real-time many-core embedded systems

On-chip interconnection networks (OCINs) in many-core embedded systems consume large portions of the chip’s area, cost, delay and power. In addition to competing in area, cost, and power, OCINs must feature low diameters to meet real time deadlines. To achieve these goals, designing low-latency networks and sharing network resources are essential. We explore 13 OCINs – some are new such as the Enhanced Kite and the Spidergon–Donut networks – in 64-core systems with various topologies and properties. We also derive and compare their worst case delays, longest and average distances, critical link lengths, bisection bandwidths, total link and router costs, and total arbiter powers. Results indicate that the Enhanced Kite, Kite, Spidergon–Donut and Spidergon–Donut4 stand out in best worst-case delays with the Spidergon–Donut4 additionally featuring lower link and router costs, total arbiter power, and better 2D implementation and scalability.

New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip

A new theory for deadlock-free multicast routing especially used for on-chip interconnection network (NoC) is presented in this paper. The NoC router hardware solution that enables the deadlock-free multicast routing without utilizing virtual channels is introduced formally. The special characteristic of the NoC is that, wormhole packets can cut-through at flit-level and can be interleaved in the same channel with other flits of different packets by multiplexing it using a rotating flit-by-flit arbitration. The routing paths of each flit can be guaranteed correct because flits belonging to the same packet are labeled with the same local Id-tag on every communication channel. Hence, multicast deadlock problem can be solved at each router by further applying a hold-release tagging mechanism to control and manage conflicting multicast requests.

Low-Power, Resilient Interconnection with Orthogonal Latin Squares

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability.

An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing

QAM is a widely used multilevel modulation technique, with a variety of applications in data radio communication systems. Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications. This work presents the architecture of a highly parallel QAM modulator, using MPSoC-based design flow and design methodology, which offers multirate modulation. The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks, offering high data rates (more than 1 Gbps), even at low modulation levels (16-QAM). Furthermore, the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance, depending on the on-chip interconnection network congestion and run-time faults. Preliminary results from this work have been published in the Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC 2010). The current version of the work includes a detailed description of the proposed system architecture, extends the results significantly using more test cases, and investigates the impact of various design parameters. Furthermore, this work investigates the use of the hardware resource allocation algorithm as a graceful degradation mechanism, providing simulation results about the performance of the QAM in the presence of faulty components.

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

SUMMARY The on-chip interconnection network (OCIN) is an integrated solution for system-on-chip (SoC) designs. The buffer architecture and size, however, dominate the performance of OCINs and affect the design of routers. This work analyzes different buffer architectures and uses a data-link two-level FIFO (first-in first-out) buffer architecture to implement high-performance routers. The concepts of shared buffers and multiple accesses for buffers are developed using the two-level FIFO buffer architecture. The proposed two-level FIFO buffer architecture increases the utilities of the storage elements via the centralized buffer organization and reduces the area and power consumption of routers to achieve the same performance achieved by other buffer architectures. Depending on a cycleaccurate simulator, the proposed data-link two-level FIFO buffer can realize performance similar to that of the conventional virtual channels, while using 25% of the buffers. Consequently, the two-level FIFO buffer can achieve about 22% power reduction compared with the similar performance of the conventional virtual channels using UMC 65 nm CMOS technology.

A networks-on-chip emulation/verification framework

The emulation and functional validation are essential to the assessment of the correctness and performance of networks-on-chip architecture. A flexible hardware/software networks-on-chip open platform (NoCOP) emulation framework is designed and implemented for exploring the on-chip interconnection network architectures. An instruction set simulator and universal serial bus communicator control and configure the emulation parameters and process that are running on the host computer as active elements in the emulation framework. The experimental results show that the proposed emulation/verification framework can speed up the simulation, preserve the cycle accuracy and decrease the usage of the resources of field programmable gate array.

A Direct Coherence Protocol for Many-Core Chip Multiprocessors

Future many-core CMP designs that will integrate tens of processor cores on-chip will be constrained by area and power. Area constraints make impractical the use of a bus or a crossbar as the on-chip interconnection network, and tiled CMPs organized around a direct interconnection network will probably be the architecture of choice. Power constraints make impractical to rely on broadcasts (as, for example, Token-CMP does) or any other brute-force method for keeping cache coherence, and directory-based cache coherence protocols are currently being employed. Unfortunately, directory protocols introduce indirection to access directory information, which negatively impacts performance. In this work, we present DiCo-CMP, a novel cache coherence protocol especially suited to future many-core tiled CMP architectures. In DiCo-CMP, the task of storing up-to-date sharing information and ensuring ordered accesses for every memory block is assigned to the cache that must provide the block on a miss. Therefore, DiCo-CMP reduces the miss latency compared to a directory protocol by sending requests directly to the cache that provides the block in a cache miss. These latency reductions result in improvements in execution time of up to 6 percent, on average, over a directory protocol. In comparison with Token-CMP, our protocol only sends one request message for each cache miss, as such is able to reduce network traffic by 43 percent.

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this article, we explore the architectural-level implications of interconnection network design for CMPs with up to 128 fine-grain multithreaded cores. We evaluate and compare different network topologies using accurate simulation of the full chip, including the memory hierarchy and interconnect, and using a diverse set of scientific and engineering workloads. We find that the interconnect has a large impact on performance, as it is responsible for 60% to 75% of the miss latency. Latency, and not bandwidth, is the primary performance constraint, since, even with many threads per core and workloads with high miss rates, networks with enough bandwidth can be efficiently implemented for the system scales we consider. From the topologies we study, the flattened butterfly consistently outperforms the mesh and fat tree on all workloads, leading to performance advantages of up to 22%. We also show that considering interconnect and memory hierarchy together when designing large-scale CMPs is crucial, and neglecting either of the two can lead to incorrect conclusions. Finally, the effect of the interconnect on overall performance becomes more important as the number of cores increases, making interconnection choices especially critical when scaling up.

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

This paper proposes an efficient topology synthesis method for on-chip interconnection network based on crossbar switches. The efficiency of topology synthesis methods is often measured by two metrics—the quality of the synthesized topology and synthesis time. These two metrics are critically determined by the definition of the topology design space and the exploration method. Furthermore, an efficient representing method for the design space is required to tightly link the design space and the exploration method. Even though topology synthesis methods have actively been researched, most of the previous methods were not deep in thought for these factors. Unlike the previous methods, we propose a topology synthesis method with a careful consideration of these factors. Our method efficiently defines the design space by a technique called chained edge partitioning, in conjunction with a representing method for the points in the space, called enhanced restricted growth function. We also provide an exploration method which well incorporates with the aforementioned search space. To prove the effectiveness of our method, we compared our method with previous methods. The experimental results show that our method outperforms the compared methods by up to 49.8% and 104.6× in the quality of the synthesized topology and the synthesis time, respectively.

From $O(k^{2}N)$ to $O(N)$: A Fast and High-Capacity Eigenvalue Solver for Full-Wave Extraction of Very Large Scale On-Chip Interconnects

The wave-propagation problem in an on-chip interconnect network can be modeled as a generalized eigenvalue problem. For solving such a generalized eigenvalue problem, the computational complexity of Arnoldi iteration is at best O(k 2 N), where k is the number of dominant eigenvalues and N is the matrix size. In this paper, we reduce the computational complexity of the Arnoldi iteration for interconnect extraction from O(k 2 N) to O(N), thus paving the way for full-wave extraction of very large scale on-chip interconnects, of which a typical value of k is on the order of hundreds of thousands. Numerical and experimental results have demonstrated the accuracy and efficiency of the proposed fast eigenvalue solver.

Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects

Network-on-chip (NOC) is emerging as a revolutionary methodology to integrate numerous intellectual property blocks in a single die. It is the packet switching-based communications backbone that interconnects the components on multicore system-on-chip (SoC). A major challenge that NOC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. By incorporating error control coding schemes along the interconnects, NOC architectures are able to provide correct functionality in the presence of different sources of transient noise and yet have lower overall energy dissipation. In this paper, designs of novel joint crosstalk avoidance and triple-error-correction/quadruple-error-detection codes are proposed, and their performance is evaluated in different NOC fabrics. It is demonstrated that the proposed codes outperform other existing coding schemes in making NOC fabrics reliable and energy efficient, with lower latency.

Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism

In single-chip parallel processors, it is crucial to implement a high-throughput low-latency interconnection network to connect the on-chip components, especially the processing units and the memory units. In this paper, we propose a new mesh of trees (MoT) implementation of the interconnection network and evaluate it relative to metrics such as wire complexity, total register count, single switch delay, maximum throughput, tradeoffs between throughput and latency, and post-layout performance. We show that on-chip interconnection networks can provide higher bandwidth between processors and shared first-level cache than previously considered possible, facilitating greater scalability of memory architectures that require that. MoT is also compared, both analytically and experimentally, to some other traditional network topologies, such as hypercube, butterfly, fat trees and butterfly fat trees. When we evaluate a 64-terminal MoT network at 90-nm technology, concrete results show that MoT provides higher throughput and lower latency especially when the input traffic (or the on-chip parallelism) is high, at comparable area. A recurring problem in networking and communication is that of achieving good sustained throughput in contrast to just high theoretical peak performance that does not materialize for typical work loads. Our quantitative results demonstrate a clear advantage of the proposed MoT network in the context of single-chip parallel processing.