Abstract
Energy‐efficient and reliable channels are provided for on‐chip interconnection networks (OCINs) using a self‐calibrated voltage scaling technique with self‐corrected green (SCG) coding scheme. This self‐calibrated low‐power coding and voltage scaling technique increases reliability and reduces energy consumption simultaneously. The SCG coding is a joint bus and error correction coding scheme that provides a reliable mechanism for channels. In addition, it achieves a significant reduction in energy consumption via a joint triplication bus power model for crosstalk avoidance. Based on SCG coding scheme, the proposed self‐calibrated voltage scaling technique adjusts voltage swing for energy reduction. Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. This approach makes the channels of OCINs tolerant of transient malfunctions and realizes energy efficiency.
Highlights
As design complexity of multicore system-on-chip (SoC) continues to increase, a global approach is needed to effectively transport and manage on-chip communication traffic, and optimize wire efficiency
We propose a novel self-calibrated energyefficient and reliable channel design for on-chip interconnection networks (OCINs)
This work uses a combination of a self-calibrated voltage scaling technique and a selfcorrected green (SCG) coding scheme to overcome increasing variations and achieve energy-efficient on-chip data communication
Summary
As design complexity of multicore system-on-chip (SoC) continues to increase, a global approach is needed to effectively transport and manage on-chip communication traffic, and optimize wire efficiency. In current multicore SoC designs, reducing power consumption is the primary challenge for advanced technologies. NoC was investigated for dealing with the challenges of on-chip data communication caused by the increasing scale of next-generation SoC designs [2, 3]. Some physical effects in nanoscale technology degrade the performance and reliability of OCINs. channels in OCINs dominate the overall power consumption [8, 9]. The reliability issue for on-chip interconnections will be degraded due to noise. Circuits and interconnects degrade further due to noise with decreasing operating voltages.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
