On-chip Inductors Research Articles

Infrequent trigonal crystal system CoNb thin films: investigation of growth behavior, microstructure and magnetic properties

Magnetic films with excellent initial permeability, high resonance frequency, suitable anisotropy fields, and well compatibility are highly desirable for on-chip inductors and transformers. Here, Co90Nb10 thin films with different thicknesses are grown on Si substrates of different orientations using an electron beam evaporation technique. A rare trigonal crystal structure of the CoNb films was observed and was virtually unaffected by substrate orientation. Films grown exhibit thickness-dependent magnetic behavior: coercivity initially decreases and then increases, while the in-plane anisotropy field progressively diminishes. Meanwhile, the initial permeability increases initially before decreasing, and the resonance frequency continuously decreases as the thickness increases. The resultant Co90Nb10/Si (111)-50 nm film displays a high μi of 496 and a great fr of 2.1GHz. The improved magnetic performance originates from the smaller crystallite size, smoother surface roughness, and suitable in-plane anisotropy field. Moreover, the in-plane anisotropy transition to the out-of-plane anisotropy in the Co90Nb10 films whose thickness exceeds 70nm, which is attributed to the growth of the coarse columnar grains once the critical thickness is exceeded. This study demonstrates the correlation between the growth behavior, microstructure, and magnetic properties of CoNb thin films, presenting a new potential for utilizing Co-based thin films in high-frequency applications.

Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications

This article deals with the analysis of irregularly shaped single turn octagonal spiral inductors for millimeter-wave and sub-THz CMOS IC designs. Simulations and experimental results, along with theoretical formulations, are used to characterize these irregular structures. This article proposes a novel approach for efficient use of silicon chip area by reshaping the on-chip inductors used in millimeter wave (mm-wave) applications without compromising the performance of the inductors. Especially in CMOS RFICs when a space constraint exists in either X- or Y-direction in their layout, such reshaping can be attempted. Moreover, two novel methods of reshaping the inductors are proposed and studied thoroughly. The study of these irregular shapes has interesting conclusions, which are validated through on-wafer measurements. Certain methods of reshaping result in inductors which do not have degradation in their quality factors (Q), while other approaches degrade the Q. Based on these insights, a design methodology is proposed for designers who need to reshape their inductors to irregular structures while not compromising on the quality factor. The measurement results agree with the simulations and prove that the proposed reshaping is practically possible.

Selective metallization of polymer based on nanoscale tungsten oxide laser activators for advanced electronics

In recent years, laser-induced selective metallization (LISM) has been widely used to fabricate complex metal patterns and circuits due to its superior precision. Laser sensitizers known as laser-activated for electroless copper plating (ECP) are a significant premise in LISM. Herein, we confirmed that tungsten oxides (WO2.72, WO2.92, and WO3) exhibited excellent LISM activity due to oxygen vacancies (OVs) in their lattice. Moreover, non-stoichiometric tungsten (WO2.72, WO2.92) presented higher activity due to a higher concentration of OVs than the stoichiometric form of WO3, indicating the importance of OVs to the activity of laser sensitizers in LISM. Moreover, a higher OVs concentration in the laser sensitizer resulted in a higher LISM activity. This finding points out the direction for future laser sensitizer screening, synthesis, and development. After 30 min ECP, the square resistance of the prepared copper layer on ABS/WO2.72, ABS/WO2.92, and ABS/WO3 are 0.014, 0.035, and 0.176 Ω/sq, respectively. The nanoscale tungsten oxides with excellent LISM activity enabled the rapid fabrication of metal patterns and circuits in various scenarios, which expands the research field and application prospect of LISM technology. We demonstrate the advantages of LISM with tungsten oxides in fabricating advanced electronics. A strategy for replacing hand-wound windings in electromagnetic generators with 2D on-chip planar inductor arrays from LISM was proposed. The generated current reached a high level of 193 mA, and can be directly connected to wireless sensor networks to supply power. This work is the first research ever reporting laser sensitizers of tungsten oxides and introducing LISM technology into self-powered electronics.

A topology optimization of on-chip planar inductor based on evolutional on/off method and CMA-ES

PurposeThere are few reports that evolutional topology optimization methods are applied to the conductor geometry design problems. This paper aims to propose an evolutional topology optimization method is applied to the conductor design problems of an on-chip inductor model.Design/methodology/approachThis paper presents a topology optimization method for conductor shape designs. This method is based on the normalized Gaussian network-based evolutional on/off topology optimization method and the covariance matrix adaptation evolution strategy. As a target device, an on-chip planer inductor is used, and single- and multi-objective optimization problems are defined. These optimization problems are solved by the proposed method.FindingsThrough the single- and multi-objective optimizations of the on-chip inductor, it is shown that the conductor shapes of the inductor can be optimized based on the proposed methods.Originality/valueThe proposed topology optimization method is applicable to the conductor design problems in that the connectivity of the shapes is strongly required.

Modeling and Simulation of a Planar Permanent Magnet On-Chip Power Inductor

The on-chip integration of a power inductor together with other power converter components of small sizes and high-saturation currents, while maintaining a desired or high inductance value, is here pursued. The use of soft magnetic cores increases inductance density but results in a reduced saturation current. This article presents a 3D physical model and a magnetic circuit model for an integrated on-chip power inductor (OPI) to double the saturation current using permanent magnet (PM) material. A ~50 nH, 7.5 A spiral permanent magnet on-chip power inductor (PMOI) is here designed, and a 3D physical model is then developed and simulated using the ANSYS®/Maxwell® software package (version 2017.1). The 3D physical model simulation results agree with the presented magnetic circuit model, and show that in the example PMOI design, the addition of the PM increases the saturation current of the OPI from 4 A to 7.5 A, while the size and inductance value remain unchanged.

Fully Integrated Pneumatic-Free and Magnet-Free CMOS Ferrofluidic Platform for Comprehensive Biomolecular Processing.

This article presents a fully integrated CMOS ferrofluidic platform featuring on-chip three-electrode electrochemical cells, temperature regulators, and magnetic sensors. The proposed platform consists of 25 ferrofluidic pixels and 2 magnetic sensors. Each ferrofluidic pixel comprises a spiral inductor, a three-electrode electrochemical cell, a temperature sensor, and a localized Joule heater. Unlike pneumatic-based platforms, this ferrofluidic platform does not require an external pneumatic pump to drive droplets. Instead, the on-chip spiral inductors generate magnetic fields to manipulate the ferrofluidic droplets. Additionally, these inductors are repurposed as heat radiators. The CMOS ferrofluidic platform is implemented using a 45-nm CMOS SOI process. Theoretical analyses of ferrofluidic control and magnetic sensing are conducted to understand the relationship between ferrofluidic movement conditions and the integrated magnetic sensor. The on-chip electrochemical potentiostat is characterized using various concentrations of methylene blue solution, and the variation in the electrochemical sensor is measured. As proof of concept, biological measurements with on-chip real-time recombinase polymerase amplification (RT-RPA) are demonstrated. The proposed platform offers a fully integrated solution for ferrofluidic manipulation, sensing, and temperature regulation without the need for external bulky equipment, thereby supporting advanced biomolecular processing. While RT-RPA is used here solely for demonstration purposes, our ferrofluidic multi-functional CMOS array platform is also capable of processing a wide range of other molecular analytes. This versatility underscores the platform's potential for broad applications in molecular diagnostics and bioanalytical research.

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

A wideband low power RF Receiver Front-End for Internet-of-Things applications

This paper presents a broadband RF receiver front-end circuit that offers advantages in both area and power consumption. The design features an innovative dual-path noise-canceling Low-Noise Amplifier (LNA) circuit, achieving impedance matching and balun functionality without the need for on-chip inductors. The RF receiver front-end circuit comprises a I and Q doublebalanced quadrature passive mixers and an 25% duty-cycle LO generator. The circuit’s broadband characteristics enable it to operate across a wide range of frequency bands. It is implemented using a 65 nm CMOS process. The core circuit, including both RF and baseband signal paths, consumes a mere 12 mW of power. Test results demonstrate that the RF receiver front-end circuit achieves a conversion gain of 35–40 dB, a noise figure (NF) below 4.8 dB, and a minimum third-order intercept point (IIP3) exceeding −6.8 dBm over the 0.1–3.1 GHz frequency range. The chip’s overall footprint is compact at 0.9 mm2, with the entire RF signal path powered by a 1 V supply, offering clear advantages in terms of compactness and low power consumption.

A 6 to 18 GHz flat high gain power amplifier using mismatch-consistent MCR technique in 40-nm CMOS

This paper presents a power amplifier (PA) based on the mismatch-consistent magnetically coupled resonator (MCR) technique, which employs adjustable dual-pole to achieve a wide operating frequency range. The in-band no gain ripple condition of the proposed mismatch-consistent MCR is systematically analyzed and derived. By applying this condition to the mismatch-consistent MCR technique, the in-band gain flatness in broadband is improved. An ultra-wide wiring method for the power-combining structure is proposed to further improve the in-band gain flatness by reducing parasitic effects. Meanwhile, an active broadband matching network without any on-chip inductor is used to obtain a -11 dB input return loss (S11) across the whole bandwidth. Implemented in 40-nm CMOS process, the proposed PA achieves a saturated output power of 19.2 dBm, an output 1 dB compression point of 17.8 dBm, a peak power added efficiency of 29.7 %, and only 0.5 dB in-band gain ripple at 8.2-16.2 GHz. The amplifier achieves a 3 dB bandwidth from 6 to 18 GHz while the fractional bandwidth reaches 100 %, realizing wideband and flat frequency response.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor’s Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed.

Origami-Inspired Fabrication of High-Performance Wafer-Level Packaged Three-Dimensional Radio-Frequency Inductors

Planar radio-frequency (RF) on-chip inductors suffer from large electromagnetic losses, stemming from the low resistivity silicon substrate. Though it is well-known that 3-dimensional (3D) MEMS-based RF inductors offer significant performance enhancement by reducing the substrate proximity effects, they are prone to mechanical failures and often come without any appropriate packaging, leading to reliability issues. Herein, we report an approach to fabricate highly robust packaged 3D RF inductors, while relying on the concept of stress-induced self-assembly. By leveraging the large residual stresses in evaporated chromium thin films at low thicknesses (below 50 nm), we assemble the planar copper coils coated with chromium nano-layers into out-of-plane folded RF inductors, directly improving their <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor. Through measurements, we show more than three-fold ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 300%) improvement in the inductor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor after the bending. Considering the inherent fragility of suspended inductors, we then add a dedicated wafer-level polymer packaging to our inductors, to improve their mechanical robustness. Specifically, we coat a thick SU-8 layer using a quasi-static volumetric dispensing process, to embed the inductors without deforming them. Upon baking, the polymer layer solidifies, making the buried inductors extremely rigid. We show that though our inductors have <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factors similar to existing MEMS inductors, their low design complexity and high strength gained via polymer packaging make them stand out among the others. This packaging technique essentially paves the way for the widespread commercialization of suspended inductors, which has been hindered in the past by their poor mechanical reliability. 2023-0018

An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3

In this article, an ultra-low-voltage 2.4-GHz radio frequency (RF) receiver front-end architecture targeting the removal of output flicker noise is presented, making it possible to use zero-IF topology for narrow-band communication standards. The trans-impedance amplifier (TIA) is built on the proposed hybrid operational trans-conductance amplifier (OTA) with a switched-capacitor (SC) amplifier as the first gain stage and an active primary–secondary amplifier as the second gain stage, achieving an imperceptible flicker-noise corner frequency. With the SC gain stage, the interstage common-mode voltage can be set to 0 V, which reduces the minimum supply voltage to 0.5 V. As another benefit, dc offset compensation (DCOC) is performed inherently in the interstage sampling and coupling process. Fabricated in 28-nm RF CMOS process, the front-end prototype, including an on-chip matching inductor, occupies a die area of 0.8 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . Operating in the Industrial Scientific Medical (ISM) frequency band of 2.4 GHz with 1-MHz IF bandwidth, the front end provides a 36–40-dB conversion gain, an 11.5-dBm OIP3, and a flicker-noise corner frequency less than 10 kHz with the supply voltage ranging from 0.5 to 0.6 V. The RF impedance matching network provides passive voltage gain before the low-noise trans-conductance amplifier (LNTA), achieving a 4.5-dB noise figure (NF) with 0.8-mA biasing current in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_m$</tex-math> </inline-formula> stage. With the ultra-low supply voltage and the passive IF gain stage, the power consumption of the proposed front end is only 610 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> W under a 0.53-V supply voltage.

Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> on-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$</tex-math> </inline-formula> -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

A Fully Integrated Heterogenous Si-CMOS/GaN 500 MHz 6 V-to-18 V Boost Converter Chip

This paper presents a fully-integrated 500MHz single-switch resonant boost converter using heterogeneous integrated gallium nitride (GaN) and Si-CMOS. Seeking for high-level of integration with watt-level power delivering capabilities, the high-speed driver circuitries are implemented in Si-CMOS with customized on-chip inductors while the power switches adopt GaN devices. Two chips are co-designed and integrated using standard flip-chip process. In the proof-of-concept, a 500MHz single-switch resonant boost DC/DC converter is implemented, fabricated, and measured. The chip occupies an area of 3mm×3mm. It features V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> /V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> of 14∼20V/6V and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> of 3.98∼4.2W with 50∼100Ω loads. The obtained maximal conversion efficiency of 58% and power density of 460mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> are the highest among the similar fully-integrated state-of-the-arts.

A Compact Sixth-Order Common-Mode Noise Suppression Filter Based on 3-D Integration Technology

Based on three-dimensional (3-D) integration technology, a compact sixth-order common-mode noise suppression filter is proposed according to delay line theory. As the important parts of the filter, the on-chip inductors are established by through-silicon vias (TSVs) and the capacitors are realized by double layer interdigital structure. Compared with other relative literatures, the proposed filter has a minimized size of 0.29×0.32 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.0203 × 0.0224 λg <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). And it can suppress the common-mode noise more than 10 dB from 3.8 to 8.6 GHz or more than 20 dB from 4.45 to 7.85 GHz. Meanwhile, the differential signal insertion loss is kept less than 3dB.

A Study of the Fully On-Chip Inductor Coils for 30 MHz Power Regulation Applications in Energy Harvesting, Sensor Networks, and IoT Scenarios

A Study of the Fully On-Chip Inductor Coils for 30 MHz Power Regulation Applications in Energy Harvesting, Sensor Networks, and IoT Scenarios

Nanoscale on-chip inductors using a linearized meminductive circuit

This work presents a novel RF on-chip inductor that overcomes the problems with conventional large-sized inductors, which cannot be placed in an integrated circuit (IC) for large inductance values. The proposed inductor depends mainly on the meminductor, a new passive circuit element that has memory properties. This new circuit element is argued to be common in the nanoscale, where the dynamical properties of electrons and ions are likely to depend on the history of the system. Being nonlinear, it is shown that, by a suitable arrangement of meminductors and through appropriate initial values for their inductances, we can achieve a linear nanoscale inductor.

Superconducting NbN-Al hybrid technology for quantum devices

The high kinetic inductance of niobium nitride (NbN) thin films can be used for an implementation of compact on-chip inductances in cryoelectronic circuits. Here, for the first time, we demonstrate the implementation of a hybrid superconducting technology that includes the fabrication of standard aluminum submicron Josephson junctions and the NbN atomic layer deposition process. As an example, we fabricated and characterized a single and array of Al Josephson junctions together with NbN interconnections. The main Al Josephson junction parameters as well as NbN superconducting properties are in a good agreement with the values obtained by our standard fabrication process. The combination of technological processes for the NbN layers with Al Josephson junction allows implementing a new generation of innovative superconducting devices for different applications.

A Deep Learning Approach for Efficient Electromagnetic Analysis of On-Chip Inductor with Dummy Metal Fillings

A deep learning approach for the efficient electromagnetic analysis of an on-chip inductor with dummy metal fillings (DMFs) is proposed. By comparing different activation functions and loss functions, a deep neural network for DMF modeling is built using a smooth maximum unit activation function and log-cosh loss function. The parasitic capacitive effect of DMFs is quickly and accurately extracted though this model, and the effective permittivity can be obtained subsequently. An on-chip inductor containing DMFs with different filling densities is analyzed using this proposed method and compared with the electromagnetic simulation of entire structures. The results validate the accuracy and efficiency of this proposed method.