On-chip Implementation Research Articles

An efficient ANN SoC for detecting Alzheimer's disease based on recurrent computing

Alzheimer's Disease (AD) is an irreversible, degenerative condition that, while incurable, can have its progression slowed or impeded. While there are numerous methods utilizing neural networks for AD detection, there is a scarcity of High-performance AD detection chips. Moreover, excessively complex neural networks are not conducive to on-chip implementation and clinical applications. This study addresses the challenges of high misdiagnosis rates and significant hardware costs inherent in traditional AD detection techniques. A novel and efficient AD detection framework based on a recurrent computational strategy is proposed. The framework harnesses an Artificial Neural Network (ANN) embedded within a System on Chip (SoC) to perform sophisticated Electroencephalogram (EEG) analysis. The approach began by employing a reduced IEEE754 single-precision encoding method to hardware-encode the preprocessed EEG data, thereby minimizing the memory storage area. Next, data remapping techniques were utilized to ensure the continuity of the input data read addresses and reduce the memory access pressure during neural network computations. Subsequently, hierarchical and Processing Element (PE) reuse technologies were leveraged to perform the multiply-accumulate operations of the ANN. Finally, a step function was chosen to establish binary classification circuits dedicated to AD detection. Experimental results indicate that the optimized SoC achieves a 70 % reduction in area and a 50 % reduction in power consumption compared to traditional designs. For various neural network models, the detection model proposed in this paper incurs less overhead, with a training speed 3 to 4 times faster than other traditional models, and a high accuracy rate of 98.53 %.

Dirac Cones and Room Temperature Polariton Lasing Evidenced in an Organic Honeycomb Lattice.

Artificial 1D and 2D lattices have emerged as a powerful platform for the emulation of lattice Hamiltonians, the fundamental study of collective many-body effects, and phenomena arising from non-trivial topology. Exciton-polaritons, bosonic part-light and part-matter quasiparticles, combine pronounced nonlinearities with the possibility of on-chip implementation. In this context, organic semiconductors embedded in microcavities have proven to be versatile candidates to study nonlinear many-body physics and bosonic condensation, and in contrast to most inorganic systems, they allow the use at ambient conditions since they host ultra-stable Frenkel excitons. A well-controlled, high-quality optical lattice is implemented that accommodates light-matter quasiparticles. The realized polariton graphene presents with excellent cavity quality factors, showing distinct signatures of Dirac cone and flatband dispersions as well as polariton lasing at room temperature. This is realized by filling coupled dielectric microcavities with the fluorescent protein mCherry. The emergence of a coherent polariton condensate at ambient conditions are demonstrated, taking advantage of coupling conditions as precise and controllable as in state-of-the-art inorganic semiconductor-based systems, without the limitations of e.g. lattice matching in epitaxial growth. This progress allows straightforward extension to more complex systems, such as the study of topological phenomena in 2D lattices including topological lasers and non-Hermitian optics.

Time-space multiplexed photonic-electronic digital multiplier

Optical computing has shown immense application prospects in the post-Moore era. However, as a crucial component of logic computing, the digital multiplier can only be realized on a small scale in optics, restrained by the limited functionalities and inevitable loss of optical nonlinearity. In this paper, we propose a time-space multiplexed architecture to realize large-scale photonic-electronic digital multiplication. We experimentally demonstrate an 8×2-bit photonic-electronic digital multiplier, and the multiplication with a 32-bit number is further executed at 25 Mbit/s to demonstrate its extensibility and functionality. Moreover, the proposed architecture has the potential for on-chip implementation, and a feasible integration scheme is provided. We believe the time-space multiplexed photonic-electronic digital multiplier will open up a promising avenue for large-scale photonic digital computing.

On-Chip Photonic Detection Techniques for Non-Invasive In Situ Characterizations at the Microfluidic Scale.

Microfluidics has emerged as a robust technology for diverse applications, ranging from bio-medical diagnostics to chemical analysis. Among the different characterization techniques that can be used to analyze samples at the microfluidic scale, the coupling of photonic detection techniques and on-chip configurations is particularly advantageous due to its non-invasive nature, which permits sensitive, real-time, high throughput, and rapid analyses, taking advantage of the microfluidic special environments and reduced sample volumes. Putting a special emphasis on integrated detection schemes, this review article explores the most relevant advances in the on-chip implementation of UV-vis, near-infrared, terahertz, and X-ray-based techniques for different characterizations, ranging from punctual spectroscopic or scattering-based measurements to different types of mapping/imaging. The principles of the techniques and their interest are discussed through their application to different systems.

Microdisk modulator-assisted optical nonlinear activation functions for photonic neural networks

On-chip implementation of optical nonlinear activation functions (NAFs) is essential for realizing large-scale photonic neural chips. To improve the reconfigurability and enrich the functions of photonic neural network (PNN), an NAF unit with a unique capability of performing multiple types of NAFs is highly preferred. In this work, we propose and experimentally demonstrate a microdisk modulator (MDM)-assisted NAF unit, in which multiple types of electro-optic NAFs with a high response speed and multiple types of all-optical NAFs with a low latency and reduced power consumption are performed in a single device. The fabricated MDM has an add-drop configuration, in which a lateral PN junction is incorporated to achieve high-speed resonance wavelength tuning. With the use of the high-speed nonlinear electro-optic effect, three different kinds of electro-optic NAFs including sigmoid function, radial basis function (RBF), and negative rectified linear unit (ReLU) function are realized by exploiting the free-carrier dispersion effect on silicon. Moreover, thanks to the strong optical confinement in the disk cavity, all-optical NAFs can be performed by exploiting the thermo-optic effect on silicon. In the experiment, four different kinds of all-optical NAFs including softplus function, RBF, clamped ReLU function, and leaky ReLU function are demonstrated. With the use of the realized clamped ReLU function, a convolutional neural network is simulated to perform a handwritten digit classification benchmark task, and an accuracy as high as 98 % is demonstrated. Thanks to its strong electro-optic and thermo-optic effects, the proposed MDM provides a unique capability of performing multiple types of electro-optic and all-optical NAFs, which is potential to be served as a flexible nonlinear unit in large-scale PNN chips.

Design of a Scan Chain for Side Channel Attacks on AES Cryptosystem for Improved Security

Scan chain-based attacks are side-channel attacks focusing on one of the most significant features of hardware test circuitry. A technique called Design for Testability (DfT) involves integrating certain testability components into a hardware design. However, this creates a side channel for cryptanalysis, providing crypto devices vulnerable to scan-based attacks. Advanced Encryption Standard (AES) has been proven as the most powerful and secure symmetric encryption algorithm announced by USA Government and it outperforms all other existing cryptographic algorithms. Furthermore, the on-chip implementation of private key algorithms like AES has faced scan-based side-channel attacks. With the aim of protecting the data for secure communication, a new hybrid pipelined AES algorithm with enhanced security features is implemented. This paper proposes testing an AES core with unpredictable response compaction and bit level-masking throughout the scan chain process. A bit-level scan flipflop focused on masking as a scan protection solution for secure testing. The experimental results show that the best security is provided by the randomized addition of masked scan flipflop through the scan chain and also provides minimal design difficulty and power expansion overhead with some negligible delay measures. Thus, the proposed technique outperforms the state-of-the-art LUT-based S-box and the composite sub-byte transformation model regarding throughput rate 2 times and 15 times respectively. And security measured in the avalanche effect for the sub-pipelined model has been increased up to 95 per cent with reduced computational complexity. Also, the proposed sub-pipelined S-box utilizing a composite field arithmetic scheme achieves 7 per cent area effectiveness and 2.5 times the hardware complexity compared to the LUT-based model.

Microelectronics-compatible reduced graphene oxide based nanomechanical resonators capable of all-electrical actuation and read-out

Photolithographic patterning and deterministic transfer of reduced graphene oxide (rGO) are key innovations that can give way to cost-effective batch processing of nanoelectromechanical system (NEMS)-based resonators with high throughput. Here, by implementing the same, we report a facile fabrication process for NEMS-based resonators consisting of rGO as the active material for the structural layer. The structural properties of rGO thin film are confirmed using Raman spectroscopy and X-ray diffraction analysis. Temperature-dependent current–voltage characteristics of rGO film ensure the typical 2D Mott variable range hopping (VRH) transport with ambipolar charge conduction, further supporting the effectiveness of the fabrication process. All-electrical actuation and readout of the fabricated resonators are performed using both frequency modulation (FM) downconversion and piezoresistive mixing methods adeptly to achieve a resonance frequency of around 28–32 MHz. The fabrication process is compatible with the current microelectronic technology and can foster the prospect of on-chip implementation of rGO NEMS toward possible applications such as molecular sensors, mass detectors, etc.

Loss-Induced Violation of the Fundamental Transmittance-Asymmetry Bound in Nonlinear Complex Wave Systems.

Nonlinearity-induced asymmetric transport (AT) can be utilized for on-chip implementation of nonreciprocal devices that do not require odd-vector biasing. This scheme, however, is subject to a fundamental bound dictating that the maximum transmittance asymmetry is inversely proportional to the asymmetry intensity range (AIR) over which AT occurs. Contrary to the conventional wisdom, we show that the implementation of losses can lead to an increase of the AIR without deteriorating the AT. We develop a general theory that provides a new upper bound for AT in nonlinear complex systems and highlights the importance of their structural complexity and of losses. Our predictions are confirmed numerically and experimentally using a microwave complex network of coaxial cables.

Digital Hardware Implementation of ReSuMe Learning Algorithm for Spiking Neural Networks.

Within this paper, we demonstrate the feasibility of the FPGA implementation as well as the 180nm CMOS circuit design of a particular biologically plausible supervised learning algorithm (ReSuMe). Based on the Spike-Timing-Dependent Plasticity (STDP) learning phenomenon, this design proposes a fully configurable implementation of STDP learning window function to adjust the learning process for different applications, optimizing results for each use case. The CMOS implementation in 180nm technology node supplied with 1.8V shows a core area of 0.78mm2 and verifies the suitability of an on-chip ReSuMe learning algorithm implementation and its capability of integration with a multitude of external and already designed structures of Spiking Neural Networks (SNNs).

Oscillatory neural network learning for pattern recognition: an on-chip learning perspective and implementation.

In the human brain, learning is continuous, while currently in AI, learning algorithms are pre-trained, making the model non-evolutive and predetermined. However, even in AI models, environment and input data change over time. Thus, there is a need to study continual learning algorithms. In particular, there is a need to investigate how to implement such continual learning algorithms on-chip. In this work, we focus on Oscillatory Neural Networks (ONNs), a neuromorphic computing paradigm performing auto-associative memory tasks, like Hopfield Neural Networks (HNNs). We study the adaptability of the HNN unsupervised learning rules to on-chip learning with ONN. In addition, we propose a first solution to implement unsupervised on-chip learning using a digital ONN design. We show that the architecture enables efficient ONN on-chip learning with Hebbian and Storkey learning rules in hundreds of microseconds for networks with up to 35 fully-connected digital oscillators.

On-Chip Adaptive Implementation of Neuromorphic Spiking Sensory Systems with Self-X Capabilities

In contemporary devices, the number and diversity of sensors is increasing, thus, requiring both efficient and robust interfacing to the sensors. Implementing the interfacing systems in advanced integration technologies faces numerous issues due to manufacturing deviations, signal swings, noise, etc. The interface sensor designers escape to the time domain and digital design techniques to handle these challenges. Biology gives examples of efficient machines that have vastly outperformed conventional technology. This work pursues a neuromorphic spiking sensory system design with the same efficient style as biology. Our chip, that comprises the essential elements of the adaptive neuromorphic spiking sensory system, such as the neuron, synapse, adaptive coincidence detection (ACD), and self-adaptive spike-to-rank coding (SA-SRC), was manufactured in XFAB CMOS 0.35 μm technology via EUROPRACTICE. The main emphasis of this paper is to present the measurement outcomes of the SA-SRC on-chip, evaluating the efficacy of its adaptation scheme, and assessing its capability to produce spike orders that correspond to the temporal difference between the two spikes received at its inputs. The SA-SRC plays a crucial role in performing the primary function of the adaptive neuromorphic spiking sensory system. The measurement results of the chip confirm the simulation results of our previous work.

Resonant silicon waveguide with strong transverse electric field rotation for magnetic-field-induced non-reciprocity.

Non-reciprocal devices suitable for on-chip implementation are of high importance in modern photonics. In most cases, non-reciprocity is caused by the magneto-optical effect. At the same time, the external magnetic field is convenient to apply in the normal direction to the chip plane, which leads to Voigt geometry and modes with in-plane transverse rotations of the electric field. Here, we propose two resonant magnetic material-free silicon waveguides supporting such modes. The first one is a rectangular waveguide with air holes inside, whose modes have higher rotations at the telecom wavelength, but the silicon thickness is non-standard. The second one is based on a 220-nm-thick silicon waveguide compatible with commercially available silicon-on-insulator wafers. We also propose the scheme of an optical isolator based on a Mach-Zehnder interferometer with a rotation elements delay in its arms.

Design and Analysis of an On-Chip Current-Driven CMOS Parametric Frequency Divider

This paper introduces an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz. A custom input driver stage with a buffer enables to generate the input current of the PFD core from a digital clock signal or sinusoidal source, and a band-pass filter (BPF) stage suppresses undesirable harmonics at the output. Analyses and discussions of design considerations provide insights into the PFD’s input driving conditions, filtering characteristics of the output driver, as well as the effects of the limited quality (Q) factor of passive components and layout parasitics. A prototype chip was fabricated in standard 65-nm CMOS technology and tested. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the authors’ knowledge, the proposed PFD is the first on-chip implementation of a current-driven parametric frequency divider in a standard CMOS process with sub-6 GHz operation, which demonstrates the feasibility of on-chip integration into RF systems.

Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Pipelined analog-to-digital converters (ADCs) are fundamental components of various signal processing systems requiring high sampling rates and a high linearity. Over the past years, calibration techniques have been intensively investigated to increase the linearity. In this brief, we propose an equalization-based calibration technique which does not require knowledge of the ADC input signal for calibration. For that, a test signal and a scaled version of it are fed into the ADC sequentially, while only the corresponding output samples are used for calibration. Several test signal sources are possible, such as a signal generator (SG) or the system application (SA) itself. For the latter case, the presented method corresponds to a background calibration technique. Thus, slowly changing errors are tracked and calibrated continuously. Because of the low computational complexity of the calibration technique, it is suitable for an on-chip implementation. Ultimately, this brief contains an analysis of the stability and convergence behavior as well as simulation results.

Artificial neural network on-chip and in-pixel implementation towards pulse amplitude measurement

We present the design of an in-pixel artificial intelligence (AI) for extraction of an amplitude of a pulse generated in semiconductor detector. The AI is design with traditional multi-level perceptron scheme having 6 layers and the total number of 420 parameters. The implementation shows 0.34% measurement accuracy. The AI block is fed by the 6-bit ADC at 5 MHz sampling rate. Standard front-end is optimized for low-noise pulses carrying 1000–3000 electrons. The methodology was tested using FPGA and results are promising. The design is intended to be fabricated and verified in the prototype solution.

A 5.2 GHz Inductorless CNTFET-Based Amplifier Design Feasible for On-Chip Implementation

A 5.2 GHz Inductorless CNTFET-Based Amplifier Design Feasible for On-Chip Implementation

A memristor-based RBM circuit implementation and application in license plate image processing

License plate image processing is crucial in the field of intelligent transportation and public safety. Because of the influence of the shooting environment, imaging equipment, and other factors, the quality of the obtained license plate image is usually low, which affects the accuracy of license plate recognition. Image super-resolution reconstruction and image denoising technology not only improve image quality but also help further analysis and processing of the image. In this work, a memristive circuit of the restricted Boltzmann machine (RBM) is designed and applied in license plate image processing. The memristive circuit design mainly contains three modules: a generation module of hidden units, a reconstruction module of visible units, and a regeneration module of hidden units. The training process is transferred from software to on-chip implementation by the memristive circuit implementation. After applying license plate image super-resolution and image denoising, the effectiveness and superiority of the proposed memristive RBM circuit are verified by simulation and comparison results.

A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC–DC Conversion

To unlock the full potential of monolithic gallium nitride (GaN) power integrated circuits, this article explores the feasibility of developing efficient and reliable on-chip gate driving and level shifting solutions, which fundamentally facilitate the on-chip implementation of GaN power circuits. As results, a self-bootstrapped hybrid (SBH) gate driving scheme and its circuitry are developed, which achieve rail-to-rail dynamic gate driving in normal operation and robust static gate driving in large transient moments. Meanwhile, an auto-lock auto-break (A2) level shifting technique is proposed to convert the gate driving control signals from low-voltage (LV) to high-voltage (HV) domains, without requiring any p-type devices. This enables the on-chip operation of high-side power switches and makes synchronous rectification possible. On-chip temperature sensing is implemented to monitor junction temperature directly at low circuit complexity and power and cost overheads, facilitating thermal protection at high power density. Furthermore, on-die dead-time control is presented to optimize zero voltage switching (ZVS) for high efficiency. All the techniques and circuits are demonstrated in a monolithic asymmetrical half-bridge (AHB) power converter on a GaN-on-SOI process. It achieves direct 48V/1V dc–dc conversion with a maximum load current of 5 A and a current density of 1.1 A/mm2. Among the existing monolithic GaN power ICs capable of on-chip synchronous rectification, it achieves the shortest rising- and falling-edge gate driving delays of 11.6 and 14.0 ns. Despite running doubled numbers of on-chip power transistors and gate drivers, it only consumes 70-mW static power.

Reconfigurable Hardware Design Approach for Economic Neural Network

Hardware-based neural networks are becoming attractive because of their superior performance. One of the research challenges is to design such hardware using less area to minimize the cost of on-chip implementation. This brief proposes an area-efficient implementation of an Artificial Neural Network (ANN). The proposed method reduces the number of layers in the ANN by nearly half through a novel, dual use of some layers denoted as hidden layers. The hidden layers are non-traditional layers proposed in this brief. They are adaptable, and each such layer performs two separate functions through judicious use of different weights. Thus, each hidden or flexible layer does the work of two traditional ANN layers. The other type of layers used in the proposed design is the fixed layers that are used traditionally. The fixed layers are not flexible and serve the functionality of a single layer. The proposed design keeps the number of the fixed layers as low as possible. One or more fixed layers may still be needed for some applications besides the proposed flexible layers. The proposed method is implemented in Verilog HDL on Altera Arria 10 GX FPGA. Its area usage is only 41% of the state-of-the-art method, while its power consumption and speed overheads are small.

Integrated Maximum Power Point Tracking System for Photovoltaic Energy Harvesting Applications

The integrated circuits employed for power management in photovoltaic (PV) energy harvesting applications are required to perform an efficient maximum power point tracking (MPPT) process for maximizing the power production of the PV source during the continuously changing atmospheric conditions. Among the alternative MPPT methods, the perturbation and observation (P&O) technique has the advantages of operational and implementation simplicity. In this article, a novel PV MPPT control system for on-chip implementation of the P&O MPPT method is presented, which, compared to the past-proposed on-chip MPPT systems, has the advantage that it is implemented based on purely digital CMOS circuits without requiring the use of complex circuits, such as multipliers, sample and hold units, or analog-to-digital converters. Therefore, it can be easily implemented on-chip with low design complexity while simultaneously retaining the high-performance features of the P&O MPPT technique. The proposed PV MPPT system has been fabricated using the XFAB XH018 0.18- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS technology. The experimental results verify the successful operation of the on-chip PV MPPT control unit and its ability to achieve a high MPPT efficiency over a wide range of operating solar irradiation values.