On-chip Electrostatic Discharge Protection Circuit Research Articles

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications.

Compact ESD Protection Design for CMOS Low-Noise Amplifier

A low-noise amplifier (LNA) is the input part of a radio frequency (RF) transceiver, which is vulnerable to electrostatic discharge (ESD). When ESD events occur, they may change the original characteristics of the LNA, such as gain decrease and noise figure (NF) increase. Dual diodes (DD) with MOS-based power clamp is a traditional on-chip ESD protection circuit, but it has disadvantages of large parasitic capacitance, large turn-on resistance, large layout area, and large leakage current. Therefore, a new compact ESD protection circuit is proposed, which uses stacked diodes with embedded silicon-controlled rectifier (SDeSCR) and SCR-based power clamp to protect the LNA. The proposed design has advantages of low parasitic capacitance, low clamping voltage, high ESD robustness, and compact layout area. In this work, the ESD protection circuit and the ${K}$ -band LNA are fabricated in CMOS technology, and their RF characteristics and ESD robustness are verified.

On-Chip Gate Electrostatic Discharge Protection Design for 900 V Power Metal Oxide Semiconductor Field Effect Transistor Using Punch-Through Diode Without Degrading Switching Loss.

In order to protect the gate oxide from electrostatic discharge (ESD) in power MOSFET, the on-chip ESD protection circuits are required. Zener diode on poly silicon gate was normally used in power device because Zener diode structure was easy to merge with conditions of vertical structure without adding electrode. However, merged Zener diode can make unnecessary gate capacitance, and then switching characteristics are degraded by added capacitance. In this paper, a stacked punch-through diode (PT diode) with lower capacitance than Zener diode was designed for 900 V power MOSFET. The PT diode was consisted on doped polysilicon gate between the gate pad and the source pad. The electrical characteristics of this device was designed and analyzed by TCAD simulation and experiments. On the basis of this analysis, the stacked PT diode for ESD protection was optimized and compared with conventional Zener diode.

On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology

CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.

ESD Protection Design With Low-Capacitance Consideration for High-Speed/High-Frequency I/O Interfaces in Integrated Circuits

Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for integrated circuits (ICs). ESD protection design for giga-Hz high-speed input/output (I/O) circuits has been one of the key challenges to implement high-speed interface circuits in CMOS technology. Conventional on-chip ESD protection circuits at the I/O pads often cause unacceptable performance degradation to high-speed I/O circuits. Therefore, ESD protection circuits must be designed with minimum negative impact to the high-speed interface circuits and to sustain high enough ESD robustness. In this paper, ESD protection design considerations for high-speed I/O circuits are addressed, and the patents related to on-chip ESD protection designs for high-speed I/O circuits are presented and discussed. Keywords: Electrostatic discharge (ESD), input/output (I/O) interface, low capacitance (low-C), power-rail ESD clamp circuit, LC resonator, LC-tank, impedance cancellation, impedance isolation, impedance matching, distributed ESD protection scheme

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.

SCR Device Fabricated With Dummy-Gate Structure to Improve Turn-On Speed for Effective ESD Protection in CMOS Technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as an on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT-SCR) device has been confirmed to be significantly reduced by this double-triggered technique.

Latchup-free esd protection design with complementary substrate-triggered scr devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins.

A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers

A low loading capacitance, 0.1 pF, on-chip electrostatic discharge (ESD) protection circuit for 2000 V HBM for GaAs power amplifiers that does not degrade RF circuit performance is introduced. Its principle of operation, loading capacitance, leakage current, ESD clamping characteristics, and robustness over process variation and temperature are investigated. Finally, a case study of its application to a 5.8 GHz power amplifier used for the wireless 802.11 A local area network is discussed.

Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process

The substrate-triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits for the input, output, and power pins have been designed and verified in a 0.18-/spl mu/m salicided CMOS process. The experimental results have confirmed that the proposed substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices. The human-body-model (HBM) ESD robustness of NMOS with a device dimension of W/L=300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV with the proposed substrate-triggered design.

An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology

A novel low-trigger dual-direction on-chip electrostatic discharge (ESD) protection circuit is designed to protect integrated circuits (ICs) against ESD surges in two opposite directions. The compact ESD protection circuit features low triggering voltage (/spl sim/7.5 V), short response time (0.18-0.4 ns), symmetric deep-snap-back I-V characteristics, and low on-resistance (/spl sim//spl Omega/). It passed the 14-kV human body model (HBM) ESD test and is very area efficient (/spl sim/80 V//spl mu/m width). The new ESD protection design is particularly suitable for low-voltage or multiple-power-supply IC chips.

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 mu /sup 2/, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +or-1 and +or-10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies. >