On-chip Antenna Research Articles

Investigation and analysis of design techniques for ultra-wideband CMOS on-chip dipole antennas for 6G sub-THz applications

This article explores different techniques to improve the impedance bandwidth of on-chip dipole antennas in the sub-THz frequency range. Increasing the area of the dipole antenna has shown considerable improvement in bandwidth. However, this violates the design rule checks (DRC) of the foundry. Various topologies, such as squared-slotted dipole, meandered-slotted dipole, and straight-slotted dipole antennas, are introduced and implemented to increase the width of the on-chip antennas and thus the impedance bandwidth while meeting the DRC rules. All three topologies show better performance in terms of providing improved bandwidth. The straight-slotted technique is adopted as it offers less complexity and flexibility. The behavior of the impedances for different widths implemented by the straight-slotted topology has been analyzed in detail. A 6-strip straight-slotted dipole antenna results in an ultra-wide impedance bandwidth ranging from 76–262 GHz with a fractional bandwidth of 110% and a gain of −0.6 dBi at 159 GHz, while occupying a small silicon area of 567μm×112μm. To the best of the authors’ knowledge, this is the highest fractional bandwidth that is reported to date at these frequencies.

Over-the-Air Characterization of a Steerable Sub-THz Si Lens and On-Chip Antenna System

Over-the-Air Characterization of a Steerable Sub-THz Si Lens and On-Chip Antenna System

Millimeter-wave wideband filtering on-chip antenna based on IPD technology

ABSTRACT A millimeter-wave wideband filtering on-chip antenna is proposed in this paper. Its operation frequency covers 32 GHz to 63 GHz, and the impedance fractional bandwidth reaches 63%. Based on the corner-fed patch antenna, the antenna in this work has a quasi-omnidirectional radiation pattern, and peak efficiency reaches 91.7%. By square slotting on the four sides of the patch and cross slotting on the center of the patch, the high-order mode is suppressed, which supports the wide operating frequency range with filtering characteristics. Split ring resonators are etched on the ground to strengthen filtering characteristics. Based on thin-film integrated passive device (IPD) technology, the proposed structure is applicable to the on-chip wideband and high-efficiency antenna array.

High gain D‐band hybrid integrated on‐chip antenna based on low‐cost printed circuit board packaging technology

AbstractA high gain D‐band hybrid integrated on‐chip antenna (OCA) based on a low‐cost printed circuit board (PCB) packaging technology is analyzed and designed in a standard 40‐nm CMOS process in this paper. The proposed OCA is a hybrid structure of a slotted patch OCA with off‐chip PCB ground and off‐chip dielectric resonator (DR). The proposed OCA exhibits a simulated gain of 3.5 dBi and 53% radiation efficiency at 150 GHz. The simulated impedance bandwidth is 20 GHz. The radiation performance and impedance bandwidth of the OCA are observably improved with the proposed techniques. The proposed OCA occupies 0.52 × 0.56 mm2, and addresses the highly desirable yet challenging overall design of future low‐cost integrated millimeter‐wave (mm‐Wave) and terahertz (THz) systems, which hit the mark on cost and compatibility.

Silicon Photonics for Inter/Intra-Chip Wireless Communication Using RF On-Chip Antennas

Silicon Photonics for Inter/Intra-Chip Wireless Communication Using RF On-Chip Antennas

Exploring Terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR Integrated Circuits: Advancements and Obstacles

The text provides a description of the characteristics of several NMOS and CMOS circuit approaches, as well as an explanation of the limitations associated with each technology. Next, the CMOS domino circuit, a novel form of circuit, is explained. This entails interconnecting dynamic CMOS gates in a manner that enables the activation of all gates in the circuit simultaneously using a single clock edge. Consequently, there is no need for intricate clocking methods, allowing the dynamic gate to operate at its maximum speed. This circuit features a basic mode voltage-controlled oscillator operating at 135 GHz in 80-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR, a 405 GHz push-push voltage controller in 38-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR with an on-chip patch antenna, a 128 GHz Schottky diode frequency doubler, a 170 GHz Schottky diode detector, a 600 GHz plasma wave detector in 122-nm COMPLEMENTARY METAL OXIDE SEMICONDUCTOR and a 40 GHz phase-locked loop with a frequency doubled output at 110 GHz. Given this and the trends in performance of n METAL OXIDE SEMICONDUCTOR transistors and Schottky diodes produced in complementary metal-oxide semiconductors, we lay out a plan for terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR systems and circuits, highlighting critical challenges that need to be addressed. With the advent of terahertz COMPLEMENTARY METAL OXIDE SEMICONDUCTOR

On-Chip Circularly Polarized Circular Loop Antennas Utilizing 4H-SiC and GaAs Substrates in the Q/V Band.

This paper presents a comprehensive assessment of the performance of on-chip circularly polarized (CP) circular loop antennas that have been designed and fabricated to operate in the Q/V frequency band. The proposed antenna design incorporates two concentric loops, with the outer loop as the active element and the inner loop enhancing the CP bandwidth. The study utilizes gallium arsenide (GaAs) and silicon carbide (4H-SiC) semiconductor wafer substrates. The measured results highlight the successful achievement of impedance matching at 40 GHz and 44 GHz for the 4H-SiC and GaAs substrates, respectively. Furthermore, both cases yield an axial ratio (AR) of less than 3 dB, with variations in bandwidths and frequency bands contingent upon the dielectric constant of the respective substrate material. Moreover, the outcomes confirm that utilizing 4H-SiC substrates results in a significantly higher radiation efficiency of 95%, owing to lower substrate losses. In pursuit of these findings, a 4-element circularly polarized loop array antenna has been fabricated for operation at 40 GHz, employing a 4H-SiC wafer as a low-loss substrate. The results underscore the antenna's remarkable performance, exemplified by a broadside gain of approximately 9.7 dBic and a total efficiency of circa 92%. A close agreement has been achieved between simulated and measured results.

A $V$-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700

A $V$-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700

Application of intermediate CMOS layer-based defected ground structure to design a dual-band on-chip antenna with improved gain

Application of intermediate CMOS layer-based defected ground structure to design a dual-band on-chip antenna with improved gain

A 223–276-GHz Cascadable FMCW Transceiver in 130-nm SiGe BiCMOS for Scalable MIMO Radar Arrays

This article reports a 223–276-GHz monostatic frequency-modulated continuous-wave (FMCW) radar transceiver (TRX) chip. The TRX is suitable for building massive multiple-input multiple-output (MIMO) radar arrays in the daisy-chain topology because of its cascadable feature based on the injection-locking feedthrough technique. The TRX is based on 18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> frequency multiplication chain that can be fed by either an external signal generator (SG) or its internal voltage-controlled oscillator (VCO). The modulation bandwidth (BW) is about 53 GHz when the internal VCO is activated, resulting in a range resolution of better than 3 mm. The peak output power is 3.1 dBm at 240 GHz with a 3-dB BW of 41 GHz. Its receiver (RX) channel is based on the in-phase/quadrature architecture enabling complex signal sampling. The minimum single-sideband (SSB) noise figure (NF) is 18.7 dB at 255 GHz, and the average value is 20.7 dB. The TRX chip includes an on-chip antenna coupled with a silicon lens, offering a peak effective isotropic radiated power (EIRP) of 27 dBm at 240 GHz. The TRX consumes a dc current of 234 and 270.1 mA from a single supply voltage of 3.3 V for external and internal VCO operations, respectively. The chip occupies a total area of 2.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (2.16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1.26 mm).

One hundred fifty GHz folded dipole antenna‐on‐chip based on artificial magnetic conductor structure

AbstractA folded dipole antenna using an artificial magnetic conductor (AMC) structure is proposed to improve the frequency bandwidth and reduce the size of the antenna on a chip. To change the distribution of the electromagnetic (EM) field, the proposed AMC structure shaped with square‐in‐square rings (SSRs) is arranged along the radiating metal of the folded dipole antenna and implemented on the lowermost metal layer of the backend oxide layers (BEOLs) between the radiating metal of the top layer of the BEOL and the ground plane of the bottom of the substrate. The SSR of the proposed antenna‐on‐chip (AoC) widens the frequency bandwidth by varying the electrical length to the ground and reduces the physical size of the radiating metal by increasing the effective permittivity. The 3D EM‐wave simulation shows that the proposed AMC structure changes the distribution of EM‐wave in the BEOL and Si substrate such that more EM fields are condensed around the radiating metal and the electrical length to the ground is nonuniform and longer. The AoC with the proposed AMC structure was fabricated using a 65‐nm standard complementary metal‐oxide semiconductor process with one‐poly and nine‐metal. Compared with the conventional 150‐GHz antenna that was implemented on the same die, the proposed differential antenna was measured to be a −10 dB bandwidth of 46 GHz, with a 1.12‐times improvement, and a size reduction of 20.4%. The measured gain of the proposed antenna was −5.99 dBi including the passive balun with an insertion loss of −1.36 dB in simulation.

Crosstalk suppression in CMOS terahertz detectors by using a mushroom-like AMC structure.

The suppression of the crosstalk in a CMOS THz detector is essential for enhancing the performance of detector arrays; however, it presents several technical challenges at the chip level. In this paper, a novel structure featuring a mushroom-like artificial magnetic conductor (M-AMC) is developed to suppress the crosstalk between CMOS THz detectors with on-chip antennas. Three-dimensional simulation results show that the M-AMC structure, which is designed by metal Al and doped-Si materials in the CMOS process, not only reduces the transmission coefficient of the electromagnetic wave between adjacent pixels but also enhances the electric field of the target pixels. A 0.65 THz detector array with a M-AMC structure based on the on-chip antenna was fabricated. Experimental results present that after implanting the M-AMC structure, the noise equivalent power (NEP) at the central frequency of pixels significantly decreases by 315.5%. Moreover, the distribution of NEP becomes more uniform, as evidenced by a reduction in the standard deviation coefficient of 26.3%. This demonstrates the effectiveness of the method in suppressing crosstalk and improving the responsivity of CMOS THz detectors, which can be used for high-performance THz detector arrays.

A 1 mm ×1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0–40-mM/L Detection Range With ΔΣ Backscatter Technique

Diabetes has become a leading cause of death and disability all over the world. Continuous glucose monitoring (CGM) based on wireless power transfer (WPT) and backscatter communication enables wireless real-time telemetry to control glycemic levels in a long term. However, conventional backscatter techniques in CGM systems converted the sensing current into a bit stream or a frequency signal to switch the antenna, leading to two drawbacks: 1) Large power-harvesting antennas are required to complement the power loss in data converting and antenna switching and 2) Both the resolution and detection range are limited even with a high-performance glucose sensor. In this work, we propose a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta\Sigma$</tex-math> </inline-formula> backscatter technique to demonstrate a system on die (SoD) within a 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1-mm on-chip antenna. Implemented in the 65-nm CMOS process, the proposed SoD achieves a telemetry error less than 0.25% with little impact on WPT, as well as a wide detection range of 0–40 mM/L. In vivo experimental results show that the CGM SoD realizes a resolution of 1.65 nA/mM.

The Design Methods and Experiments for a 220-GHz Quasi-Optical Cryogenic Schottky Subharmonic Mixer of High Performance

In this article, we present systematic design methods and experimental verifications of a 220-GHz quasi-optical cryogenic Schottky subharmonic mixer. To maximize device performance over a wide bandwidth and overcome the difficulties in conjugate matching designs, an impedance optimization-based cooperative design method is proposed for such quasi-optical mixer that includes the on-chip antenna and heterodyne mixing circuit. A coplanar waveguide (CPW) tuning network is utilized and optimized to offset the parasitic reactance effect of Schottky diodes. Besides, a dual-band log-periodic-slot integrated lens antenna is presented for coupling the radio frequency and local oscillator radiations with high efficiency. A reversed field tracing method is proposed to acquire the position and size of the equivalent Gaussian waists at both frequencies, thus offering the guidance for optimizing the substrate thickness and lens dimensions for improved antenna gain and radiation pattern. A 220-GHz quasi-optical mixer prototype was fabricated and experimentally verified at both room and cryogenic temperatures. At 134 K, the single-sideband noise factor and the conversion loss are around 4.2–8.5 and 6–11 dB over a wide intermediate-frequency bandwidth of 0.5–20 GHz, showing the superior device performance at the comparable bands.

Over-the-Air Noise Temperature Measurement

Noise temperature is one of the key performances of RF components, such as the amplifiers in those receivers and transmitters. It is essential to measure the noise temperature accurately; however, the traditional conduction method is no longer suitable for those components with integrated antennas, e.g., antennas in packages (AiP) or antenna on chip (AoC). This paper proposes a solution for noise temperature measurement based on the over-the-air (OTA) method. First, the concept and the problem of noise temperature for those devices integrated with RF components and radiation elements are reviewed, the proposed OTA noise temperature measurement and calibration methods are presented, the measurement systems are set up and at both C band and millimeter-wave band with different measurement distances under both transmitting and receiving states are demonstrated in detail, and the measured results are compared and discussed which verifies that this proposed method is technically feasible for the OTA noise temperatures with high accuracy.

300-GHz-Band Four-Element CMOS-InP Hybrid Phased-Array Transmitter With 36circ Steering Range

This letter presents a 300-GHz-band four-element phased-array transmitter (TX) consisting of two types of chips, CMOS and InP HBT, to achieve a high equivalent isotropically radiated power (EIRP) and wide beam coverage. The CMOS chips include mixers and control circuits for the phased-array operation and the InP HBT chips include 300-GHz-band power amplifiers (PAs) and Antipodal Vivaldi on-chip antennas. The two types of chips are connected in a flip-chip-on-chip fashion to reduce losses. A method utilizing grating lobes is devised to overcome the limited main lobe steering range. The fabricated TX achieves a maximum EIRP of 8.4 dBm with a steering range of 36 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> , which is the widest among the 300-GHz-band TXs that can handle a high modulation order. The TX also demonstrates the first-ever wireless data transmission with beam steering in the 300-GHz band and achieves a maximum data rate of 30 Gb/s over a 50-cm distance.

Miniaturized slot loaded on-chip loop antenna with multi-fingered inner loop for implantable devices

Miniaturized slot loaded on-chip loop antenna with multi-fingered inner loop for implantable devices

Proactive flow control using adaptive beam forming for smart intra-layer data communication in wireless network on chip

Systems-on-chips need numerous predesigned cores to advance. NoC enables Multi-Core SoCs (MC_SoCs). Conventional NoC cores use power and latency on multi-hop wired connections. An effective Wireless Network-on-Chip (WiNoC) architecture can overcome NoC difficulties. On-chip antennas, transceivers, and routers replace multi-hop cable connections with high-bandwidth single-hop wireless networks using WiNoC. Nanotechnology development demands fast data transfer to overcome performance bottlenecks from sharing memory modules and connecting fabrics. This research offers a new Proactive Flow control using Adaptive Beam formation for Smart Intra-layer Data Communication technique(PF_SDC) to optimally use network resources and assure QoS in Wireless Network-on-Chip for next-generation nano-domain technology. Hybrid NoC architecture optimises application admission for data transfer over wired and wireless interconnects. Data traffic is managed by a fuzzy inference-based Intelligent Head Agent (IHA). Queue load predicts router status for the fittest path selection. IHA initiates beams at angles to admit data flow towards the target while utilising the least amount of network power and resources. A simulation model shows that the proposed system may be applied in real-world applications and consumes little power with good throughput.

Improving the Performance of Antenna-on-Chip by Effectively Illuminating the Artificial Magnetic Conductors Through Coupling Enhancement Structures

An antenna-on-chip (AoC) suffers from low radiation efficiency and gain because of the highly conductive silicon substrate used in standard complementary metal–oxide–semiconductor (CMOS) processes. Placing an artificial magnetic conductor (AMC) surface underneath the AoC not only isolates the antenna from the lossy substrate but also boosts its performance through in-phase reflection. Ideally, the AMC, which has a periodic structure, should be infinite in size, but practical chip sizes limit its dimensions. The gain of an AMC-backed AoC shows a positive correlation with the AMC lateral area. However, in the ultrathin stack-up of standard CMOS processes, the AMC cannot be irradiated uniformly by the antenna because of the physical illumination issue, so the AoC gain does not increase with the AMC area after the initial increase. To improve the illumination of the AMC by an AoC, this work introduces coupling enhancement structures (CES) that employ the available metal layers of the stack-up. The proposed AMC-backed AoC with CES demonstrates a gain of 9.8 dBi and radiation efficiency of 71% at 94 GHz, which are improvements of 4.3 dB in gain and 23% in radiation efficiency, respectively, compared to an AoC backed by a conventional AMC.

A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology

This article demonstrates a fully integrated broadband four-channel phased array transceiver, capable of wireless data rates up to 200 Gb/s covering the entire <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band (110–170 GHz). The circuit is developed in a 130-nm SiGe BiCMOS technology, featuring ft/ fmax of 300/500 GHz, and includes localized back-side etching-based ON-chip patch antennas. In both transmit and receive modes, direct up-and down-conversions are performed by in-phase and quadrature mixers driven by a multiplier-by-four local oscillator chain. A bidirectional true time delay circuit, with a resolution of 0.446 ps, which is equivalent to the accuracy of a 4-bit phase shifter, provides the squint-free beam-steering capability. Beam-steering measurements show how the beam can be steered from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> to 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> in a 7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> step. The transceiver achieves a 3-dB baseband bandwidth of 30 and 27 GHz in the transmit and receive modes, respectively. A wireless link demonstration is performed by mounting two chips on printed circuit boards, one in the transmit and one in the receive mode, together with plastic lenses on both sides, at a distance of 15 cm. Hardware-in-the-loop measurements show record data rates of 180 Gb/s with EVM of 12.2% using 16-QAM and 200 Gb/s with 8.3% EVM using 32-QAM. The four-channel transceiver consumes 1.95 and 2.5 W in the receive and transmit modes, respectively, which correspond to power efficiencies of 9.75 pJ/bit in the receiver mode and 12.5 pJ/bit in the transmitter mode.