On-chip Antenna Research Articles

Design and Operation of a Graphene-Based Plasmonic Nano-Antenna Array for Communication in the Terahertz Band

Terahertz (THz)-band (0.1 - 10 THz) communication is envisioned as a key wireless technology to satisfy the need for higher wireless data rates in denser networks. Several ongoing approaches are being considered to overcome the grand challenge of the THz band, i.e., the limited communication distance. Among others, the use of new 2D nanomaterials such as graphene to create novel plasmonic devices that operate directly in the THz range and can be densely packed has been proposed. This paper presents a novel THz plasmonic array architecture which leverages the properties of graphene to greatly simplify its design and operation. Each element of the plasmonic array is an independent front-end, consisting of an on-chip plasmonic source, modulator and antenna. The advantages of this array architecture over conventional array architectures are discussed. The trade-offs in the design of the front-end and the array are exhaustively studied in transmission. The ability to perform continuous dynamic beamforming is presented. A new tailored algorithm is developed for beamforming weight selection. Extensive numerical results are provided to demonstrate the functionality of the array for dynamic beamforming and increased power output.

Design and Characterization of a 10 × 10 Pixel Array THz Camera in 350 nm CMOS Technology

In this paper, a $10\times 10$ pixel array camera for room-temperature THz imaging application in 350 nm CMOS technology is presented. The camera consists of a $10\times 10$ focal-plane array (FPA) of THz detectors, on-chip column amplifiers, digital-to-analog converter (DAC) and on-chip memory for per-pixel calibration. High performance THz detectors are realized by integrating on-chip antennas and sub-threshold Si MOSFETs. The detectors are biased with a current source for increased responsivity and improved NEP. Our designed detector improves responsivity and NEP by a factor of 900 and 7, respectively, compared to conventional photo-voltaic (cold) FET-based detector in the same technology node and detection settings. Additionally, we proposed a successive-approximation (SA) calibration scheme to adjust the operating point of the pixels to maximize the THz response and improve uniformity, in the presence of pixel-to-pixel process variation. At 200 GHz illunimation frequency, the average responsivity and NEP of the 2D imager are measured as 16.4 kV/W and $216~\frac {nW}{\sqrt {Hz}}$ , respectively, with an image acquisition rate of 2 Hz. The responsivity and NEP of a representative pixel are extrapolated to 10 KHz (where 1/f noise has substantially decreased) for comparison with literature. The extrapolated values are 19 kV/W and $535~\frac {pW}{\sqrt {Hz}}$ , respectively. By placing the THz camera in an optical setup, we were able to acquire images of concealed metal objects in a cardboard box at 200 GHz illumination frequency.

A Multiport Chip-Scale Dielectric Resonator Antenna for CMOS THz Transmitters

The practicality of terahertz (THz) CMOS radiating transmitters is limited by the power produced by CMOS circuits above the transistor fmax and the efficiency of on-chip antennas due to silicon substrate conductance and dimension sensitivity. In this article, we propose a new way of designing CMOS transmitters at THz frequencies by considering the silicon substrate as a dielectric resonator antenna. It is shown that sizing the substrate is the main contributor to determine the transmitter directivity and efficiency. We further propose a dense multiport approach to increase the radiated power from the silicon chip. To demonstrate the validity of this approach, a 1.45 x 1.45 mm 2 65-nm CMOS chip was designed with a 5 x 6 dense array of excitation ports implemented using injection-locked third-harmonic voltage-controlled oscillators with digital control. The measured chip achieves a record radiated power of +9 dBm, an equivalent isotropic radiated power (EIRP) of +24 dBm, and the total power efficiency of 1.9% at 0.28 THz.

On-Chip Inductor in 0.18-μm CMOS for Low-Cost Fully Integrated Contactless Powered Sensors

Contactless sensors with CMOS on-chip antennas use only the top thick metal for the polarization antenna due to the low inductance contribution of the bottom (thin) CMOS metals adding only resistance to the antenna. In this letter, a two-layer inductor (thick top metal layer inductor in series with the bottom thin four-layer metal inductor) configuration was proposed for wireless polarization (by electromagnetic induction). The design proposed was simulated and fabricated in a 0.18- $\mu \text{m}$ CMOS process. The on-chip inductor powers a chip with a 1-mW load at a distance of 2 mm coupled with an external wireless power transmitter at 13.5 MHz with a 30-dBm output. The two-layer inductor configuration reduces the area required for the on-chip inductor by 38% and increases the on-chip inductor quality factor by 25% compared with a single-layer configuration, thus reducing the cost of fabricating fully integrated contactless sensors using only CMOS technologies.

Multiband Dual-Meander Line Antenna for Body-Centric Networks’ Biomedical Applications by Using UMC 180 nm

A new, compact, on-chip antenna architecture for 5G body-centric networks’ (BCNs) applications is presented in this paper. The integrated antenna combines two turns of dual-meander lines (DML) on two stacked layers and a metal ground layer. The proposed DML antenna structure operated at resonant bands 22 GHz, 34 GHz, 44 GHz, and 58 GHz with an operating bandwidth up to 2 GHz at impedance bandwidth ≤−7.5 dB (VSWR—Voltage Standing Wave Ratio ≤ 2.5) and antenna gain about −20 dBi, −15 dBi, −10 dBi, and −1 dBi, respectively. Then it was compared with conventional single-meander line antenna. The proposed structure decreased the resonant frequency by 22%, increased number of tuning bands, and broadened the operating bandwidth by 25%, 15%, 10%, and 20% for the tuning bands to be a suitable choice for high-data -ate biomedical applications. Furthermore, the proposed antenna was simulated and studied for its performance on and inside the human body to test the integration effect in wearable equipment. The results showed that the antenna had acceptable performance in both locations. All simulations of the proposed antenna were done were done by using Ansys HFSS (high-frequency structure simulator) v.15 (Ansys, Canonsburg, PA, USA). The DML (Digital Microwave Links) antenna was fabricated by using UMC (United Microelectronics Corporation) 180 nm CMOS (Complementary Metal–Oxidesemi–Conductor) technology with a total area of 1150 µm × 200 µm and the results showed a good agreement between measured and simulated results.

Corrections to “Low-Cost Packaging of 300 GHz Integrated Circuits With an On-Chip Patch Antenna”

Corrections to “Low-Cost Packaging of 300 GHz Integrated Circuits With an On-Chip Patch Antenna”

THz CMOS On-Chip Antenna Array Using Defected Ground Structure

In this paper, we design a THz CMOS on-chip patch antenna with defected ground structure (DGS) and utilize it to implement a broadband and high gain on-chip antenna array. It is verified from the simulation that the DGS not only can increase the gain and bandwidth of the antenna element, but also can increase the isolation between the antenna elements in the on-chip array. Therefore, it allows the design of the compact 1 × 2 and 2 × 2 on-chip antenna array with high gain and broad bandwidth. The element spacing and feedline structures of the antenna array are designed and optimized by the simulations. The designed antenna element, and 1 × 2 and 2 × 2 antenna arrays are fabricated in a commercial 65 nm CMOS process. In the on-wafer measurement, they exhibit an antenna gain of 3.1 dBi, 7.2 dBi, and 8.2 dBi with a bandwidth of 14.0%, 21.3%, and 28.0% for the reflection coefficient less than −10 dB, respectively, at 300 GHz. This result corresponds to very good performance compared to the reported THz CMOS on-chip antenna array. Therefore, the designed CMOS on-chip antenna element and array using DGS in this work can be effectively applied to build low-cost and high performance THz systems, because they can be fully implemented in a conventional CMOS process without requiring any additional processes or manufacturing techniques.

Study on improvement of the performance parameters of a novel 0.41\u20130.47 THz on-chip antenna based on metasurface concept realized on 50\xa0\u03bcm GaAs-layer

A feasibility study is presented on the performance parameters of a novel on-chip antenna based on metasurface technology at terahertz band. The proposed metasurface on-chip antenna is constructed on an electrically thin high-permittivity gallium arsenide (GaAs) substrate layer. Metasurface is implemented by engraving slot-lines on an array of 11 × 11 circular patches fabricated on the top layer of the GaAs substrate and metallic via-holes implemented in the central patch of each row constituting the array, which connects the patch to the leaky-wave open-ended feeding slot-lines running underneath the patches. The slot-lines are connected to each other with a slit. A waveguide port is used to excite the array via slot-lines that couple the electromagnetic energy to the patches. The metasurface on-chip antenna is shown to exhibit an average measured gain in excess of 10 dBi and radiation efficiency above 60% over a wide frequency range from 0.41 to 0.47 THz, which is significant development over other on-chip antenna techniques reported to date. Dimensions of the antenna are 8.6 × 8.6 × 0.0503 mm3. The results show that the proposed GaAs-based metasurface on-chip antenna is viable for applications in terahertz integrated circuits.

An overview of terahertz antennas

The terahertz (THz) antennas, which have features of small size, wide frequency bandwidth and high data rate, are important devices for transmitting and receiving THz electromagnetic waves in the emerging THz systems. However, most of THz antennas suffer from relatively high loss and low fabrication precision due to their small sizes in high frequency bands of THz waves. Therefore, this paper presents a detailed overview of the most recent research on the performance improvement of THz antennas. Firstly, the development of THz antennas is briefly reviewed and the basic design ideas of THz antennas are introduced. Then, THz antennas are categorized as metallic antennas, dielectric antennas and new material antennas. After that, the latest research progress in THz photoconductive antennas, THz horn antennas, THz lens antennas, THz microstrip antennas and THz on-chip antennas are discussed. In particular, the practical difficulties for the development of THz antennas are discussed with promising approaches. In addition, this paper also presents a short review of the process technology of THz antennas. Finally, the vital challenges and the future research directions for THz antennas are presented.

On-Chip Terahertz Detector Designed with Inset-Feed Rectangular Patch Antenna and Catadioptric Lens

This study proposes an on-chip terahertz (THz) detector designed with on-chip inset-feed rectangular patch antenna and catadioptric lens. The detector incorporates a dual antenna and dual NMOSFET structure. Radiation efficiency of the antenna reached 89.4% with 6.89 dB gain by optimizing the antenna inset-feed and micro-strip line sizes. Simulated impedance was 85.55 − j19.81 Ω, and the impedance of the antenna with the ZEONEX horn-like catadioptric lens was 117.03 − j20.28 Ω. Maximum analyzed gain of two on-chip antennas with catadioptric lens was 17.14 dB resonating at 267 GHz. Maximum experimental gain of two on-chip patch antennas was 4.5 dB at 260 GHz, increasing to 10.67 dB at 250 GHz with the catadioptric lens. The proposed on-chip rectangular inset-feed patch antenna has a simple structure, compatible with CMOS processing and easily implemented. The horn-like catadioptric lens was integrated into the front end of the detector chip and hence is easily molded and manufactured, and it effectively reduced terahertz power absorption by the chip substrate. This greatly improved the detector responsivity and provided very high gain. Corresponding detector voltage responsivity with and without the lens was 95.67 kV/W with NEP = 12.8 pW/Hz0.5 at 250 GHz, and 19.2 kV/W with NEP = 67.2 pW/Hz0.5 at 260 GHz, respectively.

Spherical Dielectric Resonator Antenna Operating at 180 GHz

The characteristics of different resonance modes of a dielectric sphere (Alumina ceramic, permittivity around 10) are investigated by Mie's theory and confirmed by field simulations and by measurements. Based on the dominant transverse magnetic resonance mode of the sphere, an on-chip antenna design is proposed. The antenna for operation at 180 GHz is using a spherical dielectric resonator of Alumina ceramic with diameter of 0.6 mm. The antenna design is characterized by small chip-area consumption, high gain, and excellent radiation efficiency. Measurements confirm the simulated results.

A QPSK 110-Gb/s Polarization-Diversity MIMO Wireless Link With a 220–255 GHz Tunable LO in a SiGe HBT Technology

In this article, a polarization-diversity technique multiple-input multiple-output (MIMO) is demonstrated to double the spectral efficiency of a line-of-sight quadrature phase-shift keying (QPSK) wireless link at 220-255 GHz with a pair of highly integrated single-chip transmitter (TX) and receiver (RX) front-end modules in 0.13-μm SiGe HBT technology ( f T/ f max = 350/550 GHz) exploiting only a low-cost wire-bonded chip-on-board packaging solution for high-speed baseband (BB) signals. Both TX and RX chips accommodate two independent fundamentally operated direct-conversion in-phase and quadrature (IQ) paths with separately tunable on-chip multiplier-based (×16) local oscillator (LO) generation paths driven from a single external highly stable 13.75-16-GHz frequency synthesizer. On the RX side, a mixer-first architecture is implemented to improve the symmetry between upper and lower sidebands (USB and LSB) at the cost of an increased noise figure (NF), whereas, on the TX chip, each upconversion mixer is followed by a gain-bandwidth (BW)-limited fourstage power amplifier (PA) to support the link budget at a meter distance. Next, two independent IQ data streams from the upconversion/downconversion paths on each chip are directed to a common lens-coupled broadband on-chip slot antenna system. This way, two orthogonal circular polarizations [left-handed circular polarization (LHCP) and right-handed circular polarization (RHCP)] can be transmitted with sufficient isolation for link operation without the need for a high-speed depolarizer in the BB for any relative orientation between TX and RX modules. The antenna combined with a 9-mm diameter Si-lens provides a directivity of 23.5-27 dBi at 210-270 GHz for each of the modules. This, along with a peak radiated power of 7.5 dBm/ch from the TX module, and the cascaded conversion gain (CG)/single sideband (SSB) NF of 18/18 dB/ch for the RX module followed by a broadband amplifier (PSPL5882) from Tektronix allowed successful transmission of two independent QPSK data streams with an aggregate speed of 110 and 80 Gb/s over 1 and 2 m, respectively, at 230 GHz with a board-level limited channel BB bandwidth (BW) of 13.5 GHz.

Demonstration of Inter-Chip RF Data Transmission Using On-Chip Antennas in Silicon Photonics

This letter describes the design and the measurements of a 15 GHz monopole antenna implemented in silicon photonics for inter-chip communication. The antenna is designed in HFSS with its radiation pattern simulated. To confirm its operation and experimentally demonstrate inter-chip communication, the antenna is fabricated in a commercial Silicon Photonics fabrication process. Measurements include s-parameter using a vector network analyzer, and inter-chip data transmission between two on-chip antennas. The inter-chip data transmission is demonstrated using an off-chip photodetector directly as a transmitter as a proof-of-concept. Results indicate the feasibility of a monolithically integrated photodiode-antenna system as a transmitter.

Gain Enhancement of Millimeter-Wave On-Chip Antenna Through an Additively Manufactured Functional Package

The antenna-on-chip (AoC) presents an excellent solution for applications requiring higher integration levels and lower cost; however, its radiation performance is poor due to the inherent lossy Si substrate in conventional complementary metal–oxide–semiconductor (CMOS) processes. It is well known that every chip requires a package to protect it from the environment; however, this package does not provide any functionality, despite adding to the cost and required space. In this article, we propose a functional package that has been designed to enhance the gain of the AoC. A 71 GHz coplanar waveguide (CPW)-fed on-chip monopole antenna, driven by a voltage-controlled oscillator (VCO) and frequency doubler, was realized in the standard 0.18 $\mu \text{m}$ CMOS technology. As a first step to enhance its gain, the AoC was designed on top of an artificial magnetic conductor (AMC) surface. Further gain enhancement was achieved by transforming the chip package into a combination of a superstrate layer and a Fresnel lens, qualifying this as a system-on-package (SoP). The package has been realized through additive manufacturing to maintain the low-cost aspect. Overall, the measured gain of the packaged AoC is 6.8 dBi, which has been enhanced by ~20 dBs compared to the unpackaged antenna without an AMC layer.

Polarization-division and spatial-division shared-aperture nanopatch antenna arrays for wide-angle optical beam scanning.

Chip-based optical beam scanners hold promise for future compact high-speed light detection and ranging (LIDAR) systems. Many of the demonstrated chip-based optical beam scanners are designed based on diffraction-based waveguide gratings as on-chip antennas. The waveguide grating antenna, however, only provides a typical field-of-view (FOV) of roughly 10° by tuning the input light wavelength. In this paper, polarization-division and spatial-division multiplexed nanoantenna arrays are proposed to expand the FOV of on-chip antennas. The proposed device, based on silicon-on-insulator (SOI) platform, consists of three nanoantenna groups which are densely packed and fed by a common silicon nanostrip. It is demonstrated that the combination of the optical mode-multiplexing technique and the antenna engineering allows independent controls over the interactions between multiple nanoantenna groups and the waveguide. By proper engineering of the antenna dimensions, the proposed device achieves a FOV of over 40° within a 100 nm wavelength tuning range, almost tripling that of the conventional waveguide grating antenna.

High-Gain Metasurface in Polyimide On-Chip Antenna Based on CRLH-TL for Sub-Terahertz Integrated Circuits

This paper presents a novel on-chip antenna using standard CMOS-technology based on metasurface implemented on two-layers polyimide substrates with a thickness of 500 μm. The aluminium ground-plane with thickness of 3 μm is sandwiched between the two-layers. Concentric dielectric-rings are etched in the ground-plane under the radiation patches implemented on the top-layer. The radiation patches comprise concentric metal-rings that are arranged in a 3 × 3 matrix. The antennas are excited by coupling electromagnetic energy through the gaps of the concentric dielectric-rings in the ground-plane using a microstrip feedline created on the bottom polyimide-layer. The open-ended feedline is split in three-branches that are aligned under the radiation elements to couple the maximum energy. In this structure, the concentric metal-rings essentially act as series left-handed capacitances CL that extend the effective aperture area of the antenna without affecting its dimensions, and the concentric dielectric rings etched in the ground-plane act as shunt left-handed inductors LL, which suppress the surface-waves and reduce the substrates losses that leads to improved bandwidth and radiation properties. The overall structure behaves like a metasurface that is shown to exhibit a very large bandwidth of 0.350–0.385 THz with an average radiation gain and efficiency of 8.15dBi and 65.71%, respectively. It has dimensions of 6 × 6 × 1 mm3 that makes it suitable for on-chip implementation.

A +3-dBm-EIRP 240-GHz Circular-Polarized Radiator Utilizing a Sub-THz PA in 65-nm CMOS

We present a circular-polarized radiator in a 65-nm CMOS with a measured equivalent isotropically radiated power (EIRP) of +3 dBm at 239.2 GHz. To boost the radiating power, the subterahertz signal generated from a tripler is enhanced by a fundamental driving amplifier before being fed to an on-chip two-array patch antenna for circular-polarized radiation. A $W$ -band voltage-controlled oscillator (VCO) was codesigned with a push–pull driver to optimize the output power and efficiency. Using the frequency-tuning capability of the $W$ -band VCO, the output frequency was precisely tuned to 239.2 GHz, which provided the maximum output power of +0.5 dBm. The fabricated radiator occupies the chip area of 1.44 mm2, and it consumes dc power of 272 mW under a 1.2-V supply.

A multiple‐input‐multiple‐output on‐chip Quasi‐Yagi‐Uda antenna for multigigabit communications: Preliminary study

AbstractThis article presents a solution for the low gain and the poor efficiency of the on‐chip antennas (OCA). The four elements of Quasi‐Yagi‐Uda antennas (QYUA) are introduced based on the diversity technique to reduce the interference between the elements. In addition, these antennas achieve high isolations between them due to the use of reflector for each antenna. The QYUA is selected to improve the radiation properties of the end‐fire radiator in the millimeter‐wave range for on‐chip systems. The proposed MIMO antenna is used for the point to point communications. The complementary metal‐oxide semiconductor with 180 nm standard is used in the antenna design with six metal layers. The QYUA combines three parts (driven element, reflector, and director); the driven consists of two meander lines fed by coplanar‐slot and operates as a dipole, the reflector is an arc likes a semicircle to prevent the back radiation and increase the front to back ratio, and the director is a meander line to directive the radiation into the proposed direction (front end‐fire direction). All MIMO parameters such as envelope correlation coefficient, channel capacity loss, diversity gain, and total active reflection coefficient in addition to the different configurations of the MIMO are presented. All results are verified by computer simulation technology and high‐frequency structure simulator. The contribution of this article is the MIMO antenna design for point to point communications to serve multigiga communications systems with high data rate and high gain. This MIMO system is considered here to solve the problems of OCA designs.

TSV Antennas for Multi-Band Wireless Communication

On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. This work challenges the on-chip antenna design conventions, and pushes toward a Through-Silicon Via-based antenna design called TSV_A that establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30mm on-chip distance. The TSV_A performance is evaluated in both Finite Element Method and system-level Network-on-Chip (NoC) simulations. A comparison to traditional wire-based NoCs, analysis of wireless multi-bands, and technology scaling to demonstrate the substantial area improvements compared to traditional wireless NoCs (up to 99.88%) are performed. Simulation results show an improvement in network latency up to ~13% (average improvement of ~7%), energy-delay improvements of ~34% on average, and an improvement in throughput up to ~34% (average improvement of ~23%), using Wireless NoC with multi-band TSV_As. The improved signal performance of TSV_A, and multi-band capabilities, are ideal for wireless intercell communication for programmable metasurfaces with dedicated communication layers.

60-GHz 64- and 256-Element Dual-Polarized Dual-Beam Wafer-Scale Phased-Array Transceivers With Reticle-to-Reticle Stitching

This article presents 60-GHz $2\times 64$ - and $2 \times 256$ -element dual-polarized dual-beam wafer-scale phased-array transceivers with integrated up/downconverters. The $2\times 64$ -element phased array is built as a single reticle and occupies $21\times21$ mm2. It is based on RF beamforming transmit/receive (TRX) channels with 5-bit phase and 9-bit gain control, dual nested 1:64 distribution networks with Wilkinson divider/combiners, line amplifiers (LAs), and dual up/downconverters with a shared local-oscillator (LO) multiplier chain. The differential on-chip antenna feeds are electromagnetically (EM) coupled to a high-efficiency quartz superstrate dipole antenna array placed $\lambda $ /2 apart in the horizontal and vertical directions. Four $2\times 64$ -element phased-array reticles are then bondwire-stitched in the intermediate-frequency (IF)/LO domain to form a $2\times 256$ -element phased-array super-reticle that occupies $42\times42$ mm2. The $2\times 64$ - and $2\times 256$ -element phased arrays scan to ±50° in the elevation ( $E$ -plane) and azimuth ( $H$ -plane) planes. The equivalent isotropically radiated power (EIRP) of the $2\times 64$ -element array is 37–38 dBm with a 3-dB bandwidth of 60–64 GHz, while that of the $2\times 256$ -element array is 42–44 dBm with a 3-dB bandwidth of 61–63 GHz per polarization. A communication link using the $2\times 64$ -element array is demonstrated with quadrature phase-shift keying (QPSK), 16-quadrature amplitude modulation (QAM), and 64-QAM waveforms, reaching 12–16-Gb/s data rates per polarization at 1.3 m. To the best of our knowledge, this article presents the first fully polarimetric scalable wafer-scale phased-array transceivers using simple reticle-to-reticle stitching, resulting in the state-of-the-art functionality and complexity on a single chip.