Ohmic Contact Metallization Research Articles

Crystallized Ohmic Contact Effect in AlGaN/GaN High Electron Mobility Transistor

In this study, we investigate the grain size effect of high electron mobility transistor devices with ohmic contact metals of stacked Ti/Al/Ni/Au and Ti/Al/Mo/Au. In addition to a comparison of electrical characteristics, the ohmic contacts were also examined by a scratch test for the observation of adhesion behavior. The experimental results demonstrate that the metal grain size is strongly dependent on metal adhesion, which may lead to bonding issues. Moreover, the grain-induced lateral stress lowers the drive current and increases the off-state current owing to the degraded gate swing and transconductance of transistor switching characteristics.

Fabrication and Characteristics of Ion-implanted 4H Silicon Carbide Metal-Semiconductor Field-Effect Transistors on a P-Type Epilayer

The methods for the design and fabrication of ion-implanted 4H silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs) have been studied. The N-well regions are formed by three-fold (Sample A) and four-fold (Sample B) nitrogen ionimplantation on Si-face P-type epilayers with a net accept doping concentration of 6.5×10^15 cm^(-3) grown at american corporation Cree. The layout with testing structures has been designed. The locations of the peak concentration and the longitudinal straggles of the implanted ions are simulated by the Monte Carlo simulator TRIM. The box-like profile for the implantation layer is calculated by the Gauss expression. According to the structure of the device and the energy band for the implantation layer, the theoretical equation of the channel depth for the ion-implantation technique is given and calculated. The processes used to determine the implantation energies and doses are discussed. The experiment for ion-implanted 4H-SiC MESFETs is performed. The Ohmic and Schottky contact metals are annealed Ni/Cr alloy and Ti/Pt double-metal layers, respectively, and the pad metallization is Au. The performance of the current-voltage characteristics of the two samples of ion-implanted 4H-SiC MESFETs has been given at the end.

Optimization of Ohmic Contact Metallization Process for AlGaN/GaN High Electron Mobility Transistor

In this paper, a manufacturing process was developed for fabricating high-quality AlGaN/GaN high electron mobility transistors (HEMTs) on silicon carbide (SiC) substrates. Various conditions and processing methods regarding the ohmic contact and pre-metal-deposition etching processes were evaluated in terms of the device performance. In order to obtain a good ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallization scheme under different rapid thermal annealing (RTA) temperature and time. A -based reactive-ion etching (RIE) method was performed before the ohmic metallization, since this approach was shown to produce a better ohmic contact compared to the as-fabricated HEMTs. A HEMT with a 0.5 gate length was fabricated using this novel manufacturing process, which exhibits a maximum drain current density of 720 mA/mm and a peak transconductance of 235 mS/mm. The X-band output power density was 6.4 W/mm with a 53% power added efficiency (PAE).

Fabrication of 150-nm Al0.48In0.52As/Ga0.47In0.53As mHEMTs on GaAs substrates

High performance 150-nm gate-length metamorphic Al0.48In0.52As/Ga0.47In0.53As high electron mobility transistors (mHEMTs) with very good device performance have been successfully fabricated. A T-shaped gate is fabricated by using a combined technique of optical and e-beam photolithography, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate. The ohmic contact resistance R c is as low as 0.03 Ω·mm when using a novel ohmic contact metal system (Ni/Ge/Ti/Au). The devices exhibit excellent DC and RF performance. A peak extrinsic transconductance of 775 mS/mm and a maximum drain current density of 720 mA/mm are achieved. The unity current gain cut-off frequency (f T ) and the maximum oscillation frequency (f max) are 188.4 and 250 GHz, respectively.

Coupling coefficient calculation for GaSb-based quantum well distributed feedback lasers with laterally coupled gratings

We calculated the coupling coefficient of different types of laterally coupled distributed feedback (LC-DFB) structures with coupled-wave theory and the two-dimensional semivectorial finite difference method. Effects neglected in previous studies such as other partial waves, the ohmic contact and metal contact layers are taken into account in this calculation. The LC-DFB structure with metal gratings is especially studied due to its advantage over index-coupled structures. The dependence of coupling coefficient on structure parameters is theoretically calculated such as grating order, ridge width, thickness of the residual cladding layer, grating depth and lateral proximity of gratings to the ridge waveguide. A complex-coupled GaSb-based 2 µm LC-DFB structure is optimized to achieve a high coupling coefficient of 14.5 cm−1.

A novel method for the fabrication of AlGaN/GaN HEMTs on Si (111) substrates

In this paper, the development of a novel manufacturing process is presented for fabricating high-quality AlGaN/GaN high-electron-mobility transistors (HEMTs) on Si (111) substrates. Various material and processing approaches regarding surface passivation, gate oxide, ohmic contact metal, and post-gate annealing are evaluated in terms of device performance. In order to achieve better immunity to current collapse effects, we conducted experiments that investigate the relationship between the AlGaN/GaN HEMTs’ electrical characteristics and different passivation films by plasma-enhanced chemical vapour deposition. In order to obtain a better ohmic contact performance, we tested a Ti/Al/Ta/Au ohmic contact metallisation scheme using different annealing temperatures and annealing times to achieve a lower contact resistance, a more proper line edge definition, and a better surface morphology. A post-gate N2 rapid thermal annealing method done after the gate metallisation process has shown better DC current–voltage output, transfer characteristics, and gate–drain breakdown voltage results compared to the as-fabricated HEMTs. A HEMT with a 0.5-μm gate length, exhibiting a maximum drain current density of 750 mA/mm, a peak transconductance of 220 mS/mm, a unity-gain cut-off frequency of 24.6 GHz, and a maximum frequency of oscillation of 45.4 GHz, was fabricated using this novel manufacturing process; the X-band power performances demonstrate a 5.8-W/mm output power density and a 51 % power-added efficiency.

Laser processing of gallium nitride–based light-emitting diodes with ultraviolet picosecond laser pulses

The fabrication of optoelectronic devices such as light-emitting diodes (LEDs) typically involves photolithography steps, requiring specific lithography masks. This approach is expensive, inflexible and time consuming, in particular for prototyping. Therefore it would be attractive to replace these steps by direct writing techniques such as laser processing, which would speed up, for example the development and prototyping of new devices. Picosecond lasers provide a universal tool for material processing. Due to the short pulse length, material is removed by a process called "cold ablation," with minimal thermal damage to neighboring regions. As a result, better-defined structures with smoother and cleaner side walls can be fabricated compared to nanosecond-pulsed laser-based processing. We report on fully laser-processed planar gallium nitride-based LEDs fabricated using only ps laser processing for pattern definition and material removal. On the bare semiconductor wafer, isolation trenches and mesa structures are formed directly by ultraviolet ps laser pulse writing. For the direct deposition of patterned ohmic contact metallizations, the ps laser fabrication and subsequent use of high-resolution shadow masks is presented. Finally, the ps laser-processed LEDs are electrically and optically characterized and their characteristics compared with those of conventionally fabricated mesa LEDs.

Design, Fabrication, and Characterization of Ni/4H-SiC (0001) Schottky Diodes Array Equipped With Field Plate and Floating Guard Ring Edge Termination Structures

In this paper, a through process for a commercial fabrication of a Schottky diodes array on thick epitaxial (50 $\mu{\rm m}$ ) 4H-SiC (0001) is presented. Nickel was used as a Schottky contact, while a tri-layer of Ti/Pt/Au was considered for ohmic contact metallization. An oxide field plate edge termination and floating metal guard ring was integrated simultaneously in each device structure. Moreover, to improve the device reliability, an optimum thickness of field plate (composite layer of thermally grown oxide and plasma enhanced chemical vapor deposition oxide) was introduced. The process-induced carbon-oxides contamination was eradicated by vacuum annealing at a mild temperature. The critical values of device parameters, such as leakage current, breakdown voltage $(V_{BV})$ , Schottky barrier height $(\phi_{B})$ , ideality factor $(\eta)$ , and epitaxial doping concentration $(N_{D})$ , were obtained from experimentally measured current–voltage $(I{\hbox{--}}V)$ and capacitance–voltage $(C{\hbox{--}}V)$ characteristics. The data revealed that $\phi_{B}$ , $\eta$ , $V_{BV}$ , and reverse leakage current are 1.34 eV, 1.21, ${>}{\rm 800}~{\rm V}$ , and 900 pA (at ${-}{\rm 100}~{\rm V}$ ), respectively, which suits most commercial aspects.

A Comparative Optimization of Electrical Properties and Surface Morphology of Ti/Al/Ta/Au Ohmic Contacts in AlGaN/GaN HEMTs on Si(111), Sapphire, 4H-SiC Substrates

In the process of characterizing AlGaN/GaN HEMTs on Si (111), Sapphire, 4H-SiC substrates, various Rapid Thermal Annealing (RTA) conditions for the Ti/Al/Ta/Au ohmic contact process and the resulting surface analysis have been investigated. In order to achieve a low ohmic contact resistance (RC) and a high quality surface morphology, we tested seven steps (800 °C to 920 °C) annealing temperatures and two steps (15, 30 sec) annealing times. According to these annealing temperatures and times, the optimal ohmic resistance of 3.62 × 10-6 Ohm • cm2 on Si(111) substrate, 9.44 × 10-6 Ohm • cm2 on Sapphire substrate and 1.24 × 10-6 Ohm • cm2 on 4H-SiC substrate are obtained at an annealing temperature of 850 °C and an annealing time of 30 sec, 800 °C and an annealing time of 30 sec and 900 °C and an annealing time of 30 sec, respectively. The surface morphologies of the ohmic contact metallization at different annealing temperatures are measured using an Atomic Force Microscope (AFM). AFM morphology Root Mean Square (RMS) level determines the relationship of the annealing temperature and the annealing time for all of the samples. According to these annealing temperatures and times, the optimal ohmic surface RMS roughness of 13.4 nm on Si(111) substrate, 3.8 nm on Sapphire substrate and 2.9 nm on 4H-SiC substrate are obtained at an annealing temperature of 850 °C and an annealing time of 30 sec, 800 °C and an annealing time of 30 sec and 900 °C and an annealing time of 30 sec, respectively.

Features of producing an ohmic contact to frontal surfaces of photoconversion structures

This paper describes a technique for producing mechanically strong and high-temperature ohmic multilayer metal contacts to silicon photoconverters.

Optimization of Ohmic metal contacts for advanced GaAs-based CMOS device

Ohmic contact resistivity of a nongold Pd/Ge/Ti/Pt on highly doped molecular beam epitaxy grown n-GaAs and In0.2Ga0.8As/GaAs (∼2 × 1018 cm−3) has been investigated by varying Pd/Ge thicknesses and rapid thermal annealing (RTA) temperature/duration. An optimized Ohmic contact was obtained in the samples with Pd/Ge of 30 nm/30 nm, using RTA at 300 °C for 10 s. Low Ohmic contact resistivity of 5.4 × 10−7 Ω cm2 on n-In0.2Ga0.8As has been achieved. The mechanism of the contact resistivity reduction has been studied using the energy-dispersive x-ray spectroscopy depth profile.

Low-Temperature Bonding of GaN on Si Using a Nonalloyed Metal Ohmic Contact Layer for GaN-Based Heterogeneous Devices

A low-temperature integration process for GaN-based heterogeneous devices was demonstrated by low-temperature bonding with Cr/Au thin films. Nonalloyed Cr/Au ohmic contacts on n-type GaN were obtained by surface treatment with low-energy fast atom beams of Ar for 15 s prior to metal deposition on n-type GaN. The as-deposited Cr/Au (50/250 nm) contacts showed a smooth surface with a root-mean-square roughness of 1.8 nm. Au-Au surface-activated bonding was carried out at 150°C in ambient air after surface activation by an Ar radio-frequency plasma. The GaN/Si samples bonded at a low temperature were so strong that bulk fracture was observed after the tensile test.

Improving the Efficiency of C-si Solar Cells Through the Optimization of Emitter Profile and Low Resistance Ohmic Metal Contact

This article has been removed: please see Elsevier Policy on Article Withdrawal (http://www.elsevier.com/locate/withdrawalpolicy).Further to an investigation the International Conference on Advances Science and Contemporary Engineering 2012, Procedia Engineering, Volume 50, has been removed by the publisher due to insufficient assurances by the programme organisers that the professional ethical codes of publishing and standards were applied consistently.Where the copyright in individual papers was transferred to the publisher, these transfers are now considered null and void, and revert back to the authors.For author enquiries please contact: [email protected].

A Bondable Metallization Stack That Prevents Diffusion of Oxygen and Gold into Monolithically Integrated Circuits Operating Above 500°C

We investigate use of tantalum silicide (TaSi2, 400 nm)/platinum (Pt, 200 nm)/iridium (Ir, 200 nm)/platinum (Pt, 200 nm) as both a bond metal and a diffusion barrier to prevent oxygen (from air) and gold (from the wire bond) from infiltrating silicon carbide (SiC) monolithically integrated circuits operating above 500°C for over 1000 h in air. The TaSi2/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. It can be used directly on ohmic contact metals, dielectric insulating layers, or interconnect metal, because it adheres to silicon dioxide (SiO2), silicon nitride (Si3N4), and titanium (Ti). In this study, we investigate use of the new metallization of TaSi2/Pt/Ir/Pt (in deposition order) with TaSi2 resting on top of a Ti-SiC contact annealed at 600°C for 30 min in nitrogen, which allows the TaSi2 layer to react with the bottom platinum layer to form the Pt2Si diffusion barrier at the Pt-Ir interface. Since the iridium layer does not readily form a silicide, it prevents the silicon from migrating into the topmost platinum layer during further annealing or high-temperature integrated circuit operation. This leaves a pure platinum layer at the surface, ideal for gold wire bonding. We discuss the characteristics of the TaSi2/Pt/Ir/Pt metallization at 500°C after 10 h, 100 h, and 1000 h in air ambient and N2 ambient. Auger electron spectroscopy (AES) depth profiles of the metallization and field-emission scanning electron microscopy-focused ion beam (FESEM-FIB) cross-sections are also discussed.

Comparison of nickel silicide and aluminium ohmic contact metallizations for low-temperature quantum transport measurements

We examine nickel silicide as a viable ohmic contact metallization for low-temperature, low-magnetic-field transport measurements of atomic-scale devices in silicon. In particular, we compare a nickel silicide metallization with aluminium, a common ohmic contact for silicon devices. Nickel silicide can be formed at the low temperatures (<400°C) required for maintaining atomic precision placement in donor-based devices, and it avoids the complications found with aluminium contacts which become superconducting at cryogenic measurement temperatures. Importantly, we show that the use of nickel silicide as an ohmic contact at low temperatures does not affect the thermal equilibration of carriers nor contribute to hysteresis in a magnetic field.

Metal Reaction Doping and Ohmic Contact with Cu-Mn Electrode on Amorphous In-Ga-Zn-O Semiconductor

We investigated the microstructure and electrical properties of Cu and Cu-Mn alloy on amorphous In-Ga-Zn-O (a-IGZO) oxide semiconductor in order to explore a high performance electrode material for thin film transistors (TFTs) in advanced flat panel displays. Current-voltage measurements of metal/semiconductor contact structure showed a non-linear behavior with Cu, while a good ohmic behavior [ρC = (1.2−2.9) × 10−4 Ω·cm2] with the Cu-Mn alloy after annealing at 250°C for 1 h. Transfer and output characteristics of TFT structure also showed excellent performance with the Cu-Mn alloy. The good electrical property was due to the formation of a highly doped n+ a-IGZO layer with the carrier density of 1.4 × 1020 cm−3. The donor doping could be achieved simply by heat treatment to promote the oxidation of Mn and the reduction of a-IGZO.

Comparison of Ohmic contact resistances of n- and p-type Ge source/drain and their impact on transport characteristics of Ge metal oxide semiconductor field effect transistors

We report the results of a systematic study to understand low drive current of Ge-nMOSFET (metal–oxide–semiconductor field-effect transistor). The poor electron transport property is primarily attributed to the low dopant activation efficiency and high contact resistance. Results are supported by analyzing source/drain Ohmic metal contacts to n-type Ge using the transmission line method. Ni contacts to Ge nMOSFETs exhibit specific contact resistances of 10 − 3 –10 − 5 Ω cm 2, which is significantly higher than the 10 − 7 –10 − 8 Ω cm 2 of Ni contacts to Ge pMOSFETs. The high resistance of Ni Ohmic contacts to n-type Ge is attributed mainly to insufficient dopant activation in Ge (or high sheet resistance) and a high tunneling barrier. Results obtained in this work identify one of the root causes of the lower than expected Ge nMOSFET transport issue, advancing high mobility Ge channel technology.

Optoelectronic characterisation of an individual ZnO nanowire in contact with a micro-grid template**Project supported by the National Natural Science Foundation of China (Grant Nso. 60776010, 60940021 and 11074060); the Natural Science Foundation of Heilongjiang Province, China (Grant No. A2008-07); and the Doctoral Start-up Fund of Harbin Normal University, China.

Optoelectronic characterisation of an individual ZnO nanowire in contact with a micro-grid template has been studied. The low-cost micro-grid template made by photolithography is used to fabricate the ohmic contact metal electrodes. The current increases linearly with the bias, indicating good ohmic contacts between the nanowire and the electrodes. The resistivity of the ZnO nanowire is calculated to be 3.8 Ω·cm. We investigate the photoresponses of an individual ZnO nanowire under different light illumination using light emitting diodes (λ = 505 nm, 460 nm, 375 nm) as excitation sources in atmosphere. When individual ZnO nanowire is exposured to different light irradiation, we find that it is extremely sensitive to UV illumination; the conductance is much larger upon UV illumination than that in the dark at room temperature. This phenomenon may be related to the surface oxygen molecule adsorbtion, which indicates their potential application to the optoelectronic switching device.

Antimonide-based pN terahertz mixer diodes

High frequency pN heterojunction diodes with cutoff frequencies over 1 THz have been fabricated using narrow bandgap high-mobility semiconductors. The pN heterojunction is composed of a 30 nm thick p-type In0.27Ga0.73Sb alloy and a 130 nm thick In0.69Al0.31As0.41Sb0.59 n-layer. A high-mobility n-type InAs0.66Sb0.34 contact layer is used to connect the mesa diode to a metal Ohmic contact. These alloys have a lattice constant a0=6.2 Å and are grown on semi-insulating GaAs, a0=5.65 Å, using a buffer consisting of 1 μm of In0.21Ga0.19Al0.6Sb with a0=6.2 Å and 0.5 μm of Ga0.35Al0.65Sb with a0=6.12 Å.

Annealing temperature dependence of Ohmic contact resistance and morphology on InAlN/GaN high electron mobility transistor structures

Ti/Al/Ni/Au Ohmic contact metallization on InAlN/GaN heterostructures both with and without a thin GaN cap layer was annealed at different temperatures. The minimum transfer resistance for the contacts of 0.65 Ω mm (specific contact resistivity of 2×10−5 Ω cm2) was achieved after 800 °C annealing for structures without the GaN cap, while those with the cap exhibited their lowest resistance at higher temperatures. The contact morphology showed considerable roughening by 750 °C but the carrier mobility was stable until annealing temperatures of 850 °C. Diffuse scattering experiments showed that the morphological roughness of the InAlN/GaN interface increased as a result of annealing at these temperatures and the data were consistent with outdiffusion of Ga into the InAlN. Unpassivated high electron mobility transistors with a gate dimension of 0.7×180 μm2 were fabricated using these contacts and showed a maximum drain current of 1.3 A/mm and an extrinsic transconductance of 366 mS/mm. The presence of the GaN cap increased the effective barrier height of Ni/Au Schottky contacts from 0.91 to 1.01 eV on the heterostructure.