Offset Cancellation Technique Research Articles

A fast continuous-time demodulation circuit for a Hall sensor with stack capacitor offset cancellation technique

A fast continuous-time demodulation circuit for a Hall sensor with stack capacitor offset cancellation technique

Design of 8 -bit low power SAR ADC in 45 nm for biomedical implants

The utilisation of low power SAR (Successive Approximation Register) Analog-to-Digital Converters holds significant importance in the domain of bio-medical signal acquisition. The present study showcases the utilisation of an 8-bit CMOS SAR-ADC for integration into the analog front end of bio-signal acquisition. The focus of this technology pertains to the monitoring of implanted bio-signal devices, with a specific emphasis on ECG/EEG signals. A capacitive digital-to-analog converter (DAC) is suggested as a means to attain power consumption in the microwatt range. This approach enables comparisons to be made without any energy consumption, leading to a substantial enhancement in energy efficiency. Furthermore, a comprehensive theoretical examination of comparator offset voltages has been conducted to enhance the offset performance of the comparator operating at low supply voltage. The analysis indicates that optimization of the comparator is achieved solely through the adjustment of transistor sizes, without the implementation of any specific offset cancellation techniques. Simulations indicate that the optimization of the offset voltage to approximately 5 mV occurs when there is variation in the common-mode input voltage at a 1 V supply. The proposed Analog-to-Digital Converter (ADC) layout has been successfully executed utilizing the 45 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The Analog-to-Digital Converter (ADC) attains a Spurious-Free Dynamic Range (SFDR) of 64.02 dB and consumes 1.9 μW of power at a sampling rate of 1.1 MHz and a supply voltage of 1 V.

A Chemoresistive Gas Sensor Readout Integrated Circuit With Sensor Offset Cancellation Technique

A Chemoresistive Gas Sensor Readout Integrated Circuit With Sensor Offset Cancellation Technique

A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset

Sense amplifiers (SA) are facing increasing offset problems and amplifying problems due to mismatch of transistors and variations. This paper presents a structure that cancels the offset which is based on the delay and offset relation. The proposed structure can measure the delay of an SA due to its own offset voltage, and convert it into the length of a correction signal. The correction signal discharges the input of the SA, which reduces the voltage of the input to cancel the offset of the SA. The proposed technique can be applied to both the conventional latch-type SA (CLSA) and the current-latched SA with an NMOS footswitch (CSANF). The schematic simulations based on the 28 nm complementary metal-oxide semiconductor process show that the proposed technique can achieve a more centralized offset distribution than the CLSA and the CSANF. Moreover, the offset voltage of the two types SA can be reduced by 71.42% and 65.95%, respectively.

A 0.4 V, 6.4 nW, −75 dBm Sensitivity Fully Differential Wake-Up Receiver for WSNs Applications

This paper presents a fully differential wake-up receiver (WuRX) with ultra-low power and high sensitivity. Implementing the fully differential framework achieves differential signal processing without an off-chip balun, which achieves noise suppression and sensitivity improvement. The low voltage baseband signal processing (LVBSP) is proposed to cut down the power consumption, which is achieved by the low-voltage fast-response differential amplifier (LFDA) and the time-domain signal processing circuit. Moreover, the periodic offset cancellation technique (POCT) in the baseband circuit is proposed to alleviate the offset and low-frequency noise impacts. This WuRX is implemented in the TSMC 65-nm CMOS process occupying an active area of 0.18 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . When operating at 434 MHz, the proposed WuRX has a −75-dBm sensitivity at 250 bps while consuming 6.4 nW from 0.4 V supply voltage.

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array

A sneak current compensation scheme with offset cancellation sensing circuit (SCC-OCSC) adopting dummy bitline and wordline is proposed to resolve sneak current problem in the cross-point memory array. The sneak current degrades sensing yield because it disturbs read operation for high resistance cell, especially, by contaminating read current. Since the sneak current increases proportionally to the array size, the array size is limited to achieve the target sensing yield, which makes it hard to implement high density memory. The proposed SCC-OCSC cancels-out the sneak current through two phases. In first phase, the sneak current is sampled by connecting dummy BL or WL to the sensing circuit. In the second phase, the sneak current is compensated by subtracting the current sampled in the first phase. Furthermore, sensing yield is enhanced by applying the offset cancellation technique, sharing the same sensing circuit in the two phases. The proposed SCC-OCSCs with dummy BL and WL effectively improve read margin with generally used biasing schemes, floating and half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> schemes, respectively. In Monte-carlo simulation including post-layout sensing circuit with 65nm CMOS technology, it is verified that sensing yield is significantly improved. Thus, the array size assigned to single sensing circuit is extended up to 8-times with SCC-OCSC, leading 88% area reduction with reduced number of required sensing circuit. Performance is improved as 66% and 25% while power consumption is improved as 47% and 37%, by SCC-OCSC with dummy BL in floating scheme and SCC-OCSC with dummy WL in half-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> scheme, respectively.

Shared Offset Cancellation and Chopping Techniques to Enhance the Voltage Accuracy of Multi-Amplifier Systems for Feedback Sensing in Power Management Applications

Shared Offset Cancellation and Chopping Techniques to Enhance the Voltage Accuracy of Multi-Amplifier Systems for Feedback Sensing in Power Management Applications

A fast transient RBAOT controlled DC-DC buck converter with dual-loop DC offset cancellation technique and constant switching frequency

A fast transient ripple-based adaptive on-time (RBAOT) controlled DC-DC buck converter is presented in this paper. Firstly, for improving the output DC accuracy while keeping the fast transient response, a dual-loop DC offset cancellation technique is proposed. The fast loop ensures fast transient response, and the slow loop to compensate for the output DC offset introduced by ripple injection. Secondly, considering the parasitic resistances of the devices, the proposed switching frequency compensation technique reduces the frequency variation in steady state regardless of the input output voltage and load current condition. The proposed buck converter has been fabricated using 0.18-μm CMOS process. Measurement results show that the proposed converter has an outstanding output DC accuracy, the output offset is less than 2 mV. Moreover, the switching frequency is centered at 2 MHz with less than 1.5% variation for an output of 1.8 V and inputs ranging from 2.1 to 3.6 V. The maximum conversion efficiency is up to 94.6%, and the transient response times are 2 and 3 μs at rising and falling edges, respectively.

A Low-Power CMOS Bandgap Voltage Reference for Supply Voltages Down to 0.5 V

A voltage reference is strictly required for sensor interfaces that need to perform nonratiometric data acquisition. In this work, a voltage reference capable of working with supply voltages down to 0.5 V is presented. The voltage reference was based on a classic CMOS bandgap core, properly modified to be compatible with low-threshold or zero-threshold MOSFETs. The advantages of the proposed circuit are illustrated with theoretical analysis and supported by numerical simulations. The core was combined with a recently proposed switched capacitor, inverter-like integrator implementing offset cancellation and low-frequency noise reduction techniques. Experimental results performed on a prototype designed and fabricated using a commercial 0.18 μm CMOS process are presented. The prototype produces a reference voltage of 220 mV with a temperature sensitivity of 45 ppm/°C across a 10–50 °C temperature range. The proposed voltage reference can be used to source currents up to 100 μA with a quiescent current consumption of only 630 nA.

Offset Cancellation and Programmable Gain Design for Switched Capacitor Amplifier in Digital DC-DC Converter

This paper presents a fully differential switched capacitor amplifier with programmable gain design and offset cancellation technique used in digital DC-DC converter. To trade off the effective resolution for dynamic range of the error ADC, the gain of the switched capacitor amplifier is designed programmable that can be configured 1X, 2X, 4X or 8X. To improve system offset performance, the first stage is utilized full-differential switch-capacitor architecture conducive to common mode noise rejection and differential offset cancellation caused by charge injection. In addition, to cancel the offset brought by amplifier input stage, offset cancellation techniques are also implemented. The offset voltage is stored in calibration capacitor in sampling phase and cancels the input offset in amplification phase. This proposed circuit is simulated in 180nm 4P6M CMOS technology. From the simulation result, the offset voltage is fully cancelled. In addition, programmable gain design is also verified that dynamic adjustment accuracy in DC-DC feedback loop in X8 is superior than X1.

Analysis of State-of-the-Art Spin-Transfer-Torque Nonvolatile Flip-Flops Considering Restore Yield in the Near/Sub-Threshold Voltage Region

Recently, the leakage power consumption of Internet of Things (IoT) devices has become a main issue to be tackled, due to the fact that the scaling of process technology increases the leakage current in the IoT devices having limited battery capacity, resulting in the reduction of battery lifetime. The most effective method to extend the battery lifetime is to shut-off the device during standby mode. For this reason, spin-transfer-torque magnetic-tunnel-junction (STT-MTJ) based nonvolatile flip-flop (NVFF) is being considered as a strong candidate to store the computing data. Since there is a risk that the MTJ resistance may change during the read operation (i.e., the read disturbance problem), NVFF should consider the read disturbance problem to satisfy reliable data restoration. To date, several NVFFs have been proposed. Even though they satisfy the target restore yield of 4σ, most of them do not take the read disturbance into account. Furthermore, several recently proposed NVFFs which focus on the offset-cancellation technique to improve the restore yield have obvious limitation with decreasing the supply voltage (VDD), because the offset-cancellation technique uses switch operation in the critical path that can exacerbate the restore yield in the near/sub-threshold region. In this regard, this paper analyzes state-of-the-art STT-MTJ based NVFFs with respect to the voltage region and provides insight that a simple circuit having no offset-cancellation technique could achieve a better restore yield in the near/sub-threshold voltage region. Monte–Carlo HSPICE simulation results, using industry-compatible 28 nm model parameters, show that in case of VDD of 0.6 V, complex NVFF circuits having offset tolerance characteristic have a better restore yield, whereas in case of VDD of 0.4 V with sizing up strategy, a simple NVFF circuit having no offset tolerance characteristic has a better restore yield.

A high-linearity capacitance-to-digital converter with capacitive offset cancellation technique

A high-linearity capacitance-to-digital converter with capacitive offset cancellation technique

Measuring and calibrating of the parasitic mismatch in MEMS accelerometer based on harmonic distortion self-test

Capacitive MEMS (micro-electromechanical systems) accelerometers have inherent parasitic capacitors, the existence of which will increase the system bias-instability and non-linearity. The parasitic mismatch induced signal is indistinguishable to the sensed signal and cannot be canceled by traditional offset cancellation technique. In this paper, a method to realize the on-line measuring and calibrating of this parasitic effect is proposed, which is based on the digital harmonic distortion self-test. The effect of different parasitic mismatch on the system output response is analyzed in detail. As will show, in self-test mode, the parasitic mismatch will induce distinctive even-order harmonics. An on-chip digital self-test circuit is built to excite and measure this characteristic. According to the measured results, the parasitic mismatch of the front-end interface can be effectively tuned out whereby preserved calibrating unit. The test result shows, using proposed technique, the parasitic mismatch could be reduced in two orders of magnitude.

An early shutdown circuit for power reduction in high-precision dynamic comparators

Dynamic comparators are an essential part of low-power analog to digital converters (ADCs) and are referred to as one of the most important building blocks in mixed mode circuits. The power consumption and accuracy of dynamic comparators directly affects the overall power consumption and effective number of bits of the ADC. In this paper, an early shutdown approach is proposed to deactivate the first stage preamplifier at the suitable time. Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects. With the proposed method power consumption can be reduced in low power high precision dynamic comparators. The proposed method has been simulated in a standard 0.18 µm CMOS technology and the results confirm its effectiveness. The proposed circuit has the ability of reducing the power consumption by 21.7% in the worst case, while having little effect on the speed and accuracy in comparison with the conventional methods. The proposed comparator consumes only 47 µW while operating at 500 MHz. Furthermore, Monte Carlo evaluations showed that the standard deviation of the residual input referred offset was 620 µV.

A 93.4% Efficiency 8-mV Offset Voltage Constant On-Time Buck Converter With an Offset Cancellation Technique

In this brief a constant on–time (COT) buck converter with high efficiency and low offset voltage is presented. It was fabricated with a TSMC $0.18{\mu }\text{m}$ 1P6M CMOS process. An additional current feedback path (ACFP) technique was incorporated to avoid subharmonic oscillation of the converter without a large equivalent series resistance (ESR) capacitor, thus reducing the output voltage ripple. However, the ACFP causes an offset voltage on the converter’s output voltage dc level with loading changes. The proposed offset cancellation can remove the dc level from current sensor in ACFP. Hence, the offset voltage can be reduced through a proposed offset cancellation technique. The experimental results revealed that the offset voltage of the proposed converter is 8mV under a 0.1A to 1A loading changes. The converter’s maximum power efficiency is 93.4 %, and its output voltage ripple is less than 18mV.

Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM

In the case of dynamic random access memory (DRAM) using a voltage latched sense amplifier, various offset voltage cancellation techniques have been studied to secure the sensing margin. However, as coupling noise and process variations increase with technology scaling, it is impossible to obtain a sufficient sensing margin only by using an offset voltage cancellation technique. In addition, offset voltage cancellation techniques have several problems, such as area overhead and sensing speed slowdown at a low supply voltage. In this paper, we propose a sense amplifier that maximizes the sensing margin by boosting the reference bitline voltage during the charge sharing operation and adopting the offset voltage cancellation technique. The sensing voltage difference of the proposed sense amplifier increases by 50% or more than that of the conventional offset cancellation (OC) sense amplifier at the low supply voltage of 0.9 V, which can improve not only the sensing speed by 2 ns but also the sensing yield by 11.8%. In addition, the proposed sense amplifier achieves a stable sensing yield with a larger cell array height and thus can compensate the area overhead of 44% caused by the OC technique by decreasing the overall cell array height.

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region

For ultra-low-power Internet of Things (IoT) devices powered by batteries or energy harvesting, a nonvolatile flip-flop (NV-FF) operating in the near-threshold voltage (NTV) region has been widely studied to save both standby and active power. However, in the NTV region, the NV-FF suffers from restore yield and performance degradation due to the increase in process variation combined with the decrease in supply voltage. This paper presents a comparative analysis of the previous NV-FFs according to supply voltage scaling and suggests the design directions for implementing the NV-FF that can operate with compact area and high performance even in the NTV region. Through the comparative analysis, a novel offset-cancellation sensing-circuit (OCSC)-based NV-FF, which adopts a separate latch and sensing circuit structure and an offset-cancellation technique, is proposed. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm model parameters show that the proposed NV-FF satisfies a target restore yield with 32% area, 88% speed, and 82% energy savings in comparison with a representative NV-FF of the merged latch and sensing circuit structure.

A Fast T&amp;H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques

This paper presents a fast spinning-current Hall sensor with 568 ns overall delay for sub-microsecond overcurrent detection (OCD) in a magnetic current sensor. By combining the continuous-time chopping techniques and discrete-time dynamic offset cancellation techniques, the spinning frequency of 250 kHz does not limit the sensor speed. The proposed track-and-hold (T&H) ping-pong comparators extend the usage of auto-zeroing techniques for sensor interface applications. The design achieves a magnetic residual offset of $85~\mu \text{T}$ (mean) and $79~\mu \text{T}$ ( $1\sigma$ ), while the offset drifts only $0.68~\mu \text{T}/^{\circ }\text{C}$ (mean) and $0.27~\mu \text{T}/^{\circ }\text{C}$ ( $1\sigma$ ) from −40 °C to 150 °C. In addition, a background switched-capacitor filter breaks the limitation of high-frequency errors on conventional correlated double sampling techniques. The design thus reduces the input-referred noise to $136~\mu \text{T}_{\mathrm {rms}}$ with a bandwidth of 1.7 MHz, while consuming at least 30% less power than the other state-of-the-art designs. Moreover, the analog stress compensation with temperature coefficient (TC) correction guarantees an overall threshold error within ±4% over package stress and temperature.

A Pseudo-Constant Frequency Constant On-Time Buck Converter With Internal Current Ripple Injection and Output DC Offset Cancellation

A constant on-time buck converter with internal inductor current synthesizer and output DC offset cancellation technique is proposed. A fully integrated inductor current synthesizer based on valley voltage detector is employed to avoid system instability for constant on-time converters with low-ESR output capacitors. Moreover, the valley voltage detector could shift the emulated inductor current signal to zero valley level. In this way, the output DC offset due to ripple injection variation could be eliminated. An on-time circuit with comparator delay compensation is presented to alleviate the switching frequency variation. The small-signal model and design criteria are derived for system stability design. The circuit has been implemented with 0.18 μm BCD process. The measurement results show that the transient response is about 15.4 μs and the overshoot or undershoot voltage is less than 36 mV when the load transient between 1 A and 5 A for input voltage of 12 V and output voltage of 1.05 V. The switching frequency across load variation Δf SW /ΔI LOAD is 4.6 kHz/A at the nominal frequency of 700 kHz. The output DC offset is less than 10 mV in case of 4 A load current change.