A 12-Bit Low-Input Capacitance SAR ADC With a Rail-to-Rail Comparator

Abstract

The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.