Calibration of SAR analog-to-digital converters for expanding the sampling rate range

Abstract

Successive approximation analog to digital converters (SARs) are widely used in electronic circuits because of good performance from the power consumption, resolution and speed points of view. Leakage currents and DAC incomplete settling limits the performance of these ADCs in low and high sampling rates respectively. This limits the range of the sampling rate in which a SAR ADC can be used and so the usage of this ADC in multi-purpose SoCs. In this paper a background calibration technique is used in order to improve the range of the SAR ADC sampling rate. It is shown that by utilizing this technique, the sampling rate can be improved in a range of from 50 kHz to 1 MHz for a 10-bit SAR ADC with ENOB > 9 bit which is designed and simulated in 90 nm CMOS technology with a 1.2 V supply voltage.