A 12 bit 50MSPS low power SAR ADC in UMC 65nm technology

Abstract

The use of analog to digital converters (ADCs) is becoming well established in frequency domain applications such as radar and wireless receivers. The boundary between analog and digital signal processing is moving closer to the antenna. So for analog-to-digital converters (ADCs) of radio receivers this indicates higher sample rate, higher resolution, and lower power dissipation. The wireless receiver architectures, showing the greatest potential to meet the commercial trends, include the direct conversion receiver and the super heterodyne receiver with an ADC sampling at the intermediate frequency (IF). The SAR ADC architecture, based on the switched capacitor (SC) technique, has most successfully covered the widely separated resolution and sample rate requirements of these receiver architectures. A 12-bit resolution is chosen considering the dynamic range of input signal. To avoid common-mode errors, the SAR ADC uses a differential topology. To decrease area, power and cost while maintaining 12-bit accuracy, the Binary-Weighted (BW) capacitor array is split into two sub-BW capacitor arrays. A dynamic latch discriminates voltage differences as small as 100 μΥ while concurrently working with rail-to-rail input signals. A uni-directional switching technique is introduced to minimize the dynamic power. The SAR ADC is designed with UMC 65nm CMOS technology.