Energy-Efficient DAC Scheme Based on Unit Capacitor Switching for SAR ADCs

Abstract

With the development of Internet of Things (IoTs), the number of sensor nodes is growing rapidly. These sensors are usually passive or supplied by batteries and are usually a mixed-signal circuit. Analog to digital converter (ADC) is a core element in the sensor, and the power consumption of occupies a considerable part of the whole sensor. SAR ADC is a good candidate for the sensor due to its good energy-efficiency, medium resolution and speed. As the key part of SAR ADC, digital-to-analog converter (DAC) dominates the power consumption of the SAR ADC when dynamic comparator is employed. In order to improve the energy efficiency of the DAC, this paper proposes energy-efficient DAC scheme based on unit capacitor switching. By employing a capacitor-splitting structure and introducing a third voltage reference Vq equal to a quarter of the voltage reference Vref, the unit capacitor can be employed to generate the last bit, which in turn reduces the DAC area. Simulation results show that the proposed scheme reduces the switching energy by 99.03% and the DAC area by 87.5% compared to the conventional SAR ADC structure, which achieves good energy-efficiency and area-efficiency.