Abstract
A constant on-time buck converter with internal inductor current synthesizer and output DC offset cancellation technique is proposed. A fully integrated inductor current synthesizer based on valley voltage detector is employed to avoid system instability for constant on-time converters with low-ESR output capacitors. Moreover, the valley voltage detector could shift the emulated inductor current signal to zero valley level. In this way, the output DC offset due to ripple injection variation could be eliminated. An on-time circuit with comparator delay compensation is presented to alleviate the switching frequency variation. The small-signal model and design criteria are derived for system stability design. The circuit has been implemented with 0.18 μm BCD process. The measurement results show that the transient response is about 15.4 μs and the overshoot or undershoot voltage is less than 36 mV when the load transient between 1 A and 5 A for input voltage of 12 V and output voltage of 1.05 V. The switching frequency across load variation Δf SW /ΔI LOAD is 4.6 kHz/A at the nominal frequency of 700 kHz. The output DC offset is less than 10 mV in case of 4 A load current change.
Highlights
With the rapid development of semiconductor manufacturing technology, the power consumption of high-performance microprocessors drastically increases the supply voltage is scaled down to sub-1V
EXPERIMENTAL RESULTS The proposed constant on-time buck converter has been implemented with 0.18 μm BCD process
A low-equivalent series resistor (ESR) multilayer ceramic capacitor (MLCC) of 22 μF is adopted as the output capacitor, and the RESR is about 10 m
Summary
With the rapid development of semiconductor manufacturing technology, the power consumption of high-performance microprocessors drastically increases the supply voltage is scaled down to sub-1V. The current ripple signal VEIC is injected to the feedback loop, and superposed on the output feedback voltage VFB to generate the overall feedback information VSUM , which is compared with the reference voltage VREF to regulate the output voltage VOUT. Based on (4)-(5), the switching period of the constant on-time converter is given by Both the ramp signal VRAMP and inductor current ripple signal VRI are generated through a first-order RC filter. The circuit consisted of resistor R5 and transistors M6-M7 is adopted to generate a lower trip voltage VTOUT for a higher input voltage VIN In this way, the on-time can be kept nearly constant and the switching frequency maintains small variation
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