Offset Calibration Research Articles

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

A new background continuous‐time offset cancelation and gain calibration strategy for open‐loop residue amplifiers in high‐speed and high‐resolution ADC's

A continuous-time offset cancelation and gain calibration strategy is proposed for open-loop residue amplifiers of pipeline ADC's. Utilizing a reliable technique for detecting gain and offset error, also saving digital amounts of the signals that are resulted from the calibration loop, data conversion proceeds without any interruption. In addition, due to sharing this structure between the several RA stages in ADC, power consumption and area occupation are decreased. Also, this strategy does not require extra circuits, like replica residue amplifier or wide-bits digital processor for offset and gain-error correction. Using digital circuits results in multiplexing clock frequency; also, utilizing a unit gain and offset calibration structure for the whole RA in the main ADC results in a significant power consumption reduction. The simulations show that the input-referred offset is reduced to around 30 μV. Also, the gain calibration loop provides a gain of 8 with an error deviation less than 0.001. Post-layout simulation results are presented at all process corners and various temperatures, using HSPICE software and 0.18 μm standard CMOS technology in 14-bit 200 MS/s Pipeline ADC with 23 dB improvement in SNR and 3.9 bit in ENOB.

Inductive XY calibration method for multi-material fused filament fabrication 3D printers

In this work an optical and inductive calibration procedures for calibrating multi-material fused filament fabrication 3D printers in the x and y directions is presented. The inductive calibration is based on the principle that the inductance of a detection coil placed on the print bed changes when the (metallic) extrusion nozzle passes it. This calibration method shows a repeatability of up to 2 µm. To determine the accuracy of this calibration method, another calibration method is proposed that directly measures the position of the deposited material. During this alternative process, a calibration structure is printed on an A4-format sheet of paper using every tool. The paper is subsequently scanned using a digital scanner, and the resulting image is analyzed using an image-processing script. Using this method as a reference, it was determined that the inductive method has an accuracy of approximately 45 µm. For applications where this accuracy is sufficient, the inductive method provides a fast solution that requires little to no user interaction. For more demanding applications, the optical calibration might be the better choice, since it is more time-consuming but yields a more accurate solution. It is expected that the accurate calibration of tool offsets will reduce both the chance of poor adhesion between materials and the mixing of filaments due to local over- and under-extrusion at material interfaces.

SAR ADC for a Multimode Radar Transceiver with Offset Calibration

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure of merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from -46 mV/+50 mV to -4 mV/+4 mV when the worst case was considered.

A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed, low power, and compact prototype. The PARG scheme allows the quantization and amplification to run in parallel for a fast pipelining operation. The 6-b ADC consists of six pipelined stages with six comparators and five amplifiers in total. Such a small number of hardware reduce the overhead from the calibration and enable fully on-chip implementation. By further sharing the calibration hardware between the offset and gain calibration, the ADC with on-chip calibration only occupies 0.0166 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 28-nm CMOS. With a linearized DA for the residue amplification, the ADC achieves 34-dB signal-to-noise and distortion ratio (SNDR) with a Nyquist input with 3.3 GS/s, consuming 5.5 mW and yielding a 40.02-fJ/conversion-step Walden figure of merit (FoM).

SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of <inline-formula> <tex-math notation="LaTeX">$128\times 128$ </tex-math></inline-formula> (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2^N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm², respectively.

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

A BJT-based temperature sensor using two sub-OPAMPs Chopper ripple reduction technique with inaccuracy of ±0.25 °C (3σ) from −45 °C to 85 °C

This paper presents a BJT-based temperature sensor inaccuracy of ±0.25 °C (3σ). To handle noises in AFE and ADCs, two modified techniques are put forward, respectively. One technique utilized in the analog front end is modified choppers with two sub-OPAMPs. Two sub-OPAMPs chopped under two non-overlapped clocks with 90-degree phase difference are used to suppress the chopper ripple while removing low frequency noises. To achieve an accurate digitization, a zoom ADC which combines SAR coarse conversion and Sigma-Delta fine conversion is applied for its high resolution and energy-efficiency. One-time offset calibration is used in the OPAMP of the 1st integrator to ensure the good integrator performance. After one-point trimming, the proposed design achieves inaccuracy of ±0.25 °C (3σ) from −45 °C to +85 °C. It occupies 0.18 mm2 in a 110 nm CMOS, and draws 12.3 μA from a 3 V supply, with a conversion time of either 4 ms or 8 ms.

A time-interleaved ADC calibration technique for spectrum monitoring applications

A fully background estimation and calibration technique to reduce the spur powers caused by time-interleaved ADC architecture is presented. The estimations of mismatches are succeeded using easily generated calibration signals. The implementation details for the mismatch estimations and calibrations are provided using a 2.8 GSPS ADC and a FPGA device. Continuous operation of the spectrum monitoring applications is allowed while the mismatch estimation and the calibration process in progress. The offset mismatch calibration is realized using an adder circuit at the background and more than 10 dB spur power reduction is obtained from the proposed method. A digital multiplier circuit is used to realize the gain calibration. The timing skew calibration is fulfilled by the addition of a small offset to the DDS (Direct Digital Synthesizer) phase offset of DDC (Digital Down Converter). It is possible to get more than 6 dB power reduction at some critical spur signals after the application of proposed timing mismatch calibration technique when a single tone sine wave input is applied.

A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations

This article presents a second-order successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) with optimized noise transfer function (NTF) zeros, background inter-stage gain, and offset calibrations. The NS, realized with an error-feedback (EF) structure, takes place in the second stage of the pipeline. A single amplifier, utilized for residue handover, realizes the EF and the optimized zeros. Copies of the EF capacitors allow their rotation role for residue saving, feedback, and sampling operations, thus omitting the extra phase for the EF operation. While further incorporating a coarse SAR ADC and partial interleaving techniques, the prototype can run at high speed with low power and strong in- band noise suppression. A split-over-time architecture with level-shift-based gain calibration is introduced to ensure the robustness of the ADC, whose hardware also facilitates the offset calibration. Besides, the split second-stage ADCs also share a single comparator, thus enabling a mismatch error insensitive split-ADC architecture with a fast convergence speed of 4000 cycles. Fabricated in 28 nm CMOS, the ADC prototype runs at a 260 MHz sampling rate and retains 20 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 79.1 dB under a small over-sampling ratio (OSR) of 6.5. It consumes 3.1 mW power at a 1 V supply and yields a Schreier figure-of-merit (FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> ) of 177.2 dB.

Real-Time Tracking Algorithm for Aerial Vehicles Using Improved Convolutional Neural Network and Transfer Learning

To address the poor image feature extraction ability, excessive tracking time, and low accuracy of traditional real-time algorithms for aerial tracking of vehicle traffic, a real-time tracking algorithm using improved convolutional neural network (CNN) and transfer learning was proposed herein. In this algorithm, first, the aerial vehicle images are matched with sample images for the image offset calibration. Second, the CNN parameters are initialized by constructing a filter set, and transfer learning is employed to construct a CNN pre-training model. Third, a deep convolution feature extraction structure map is designed to extract the depth features of images. Finally, based on the depth features, the target vehicle motion model is established, the similarity between the target and candidate models is calculated, and the real-time tracking of aerial vehicles is completed. The results show that the image correction accuracy of the proposed algorithm is as high as 92&#x0025;. The algorithm yields satisfactory results in terms of feature extraction and calculation accuracy. Moreover, it has a small overall error, the average tracking time required by it is only 22.8 s, and its false negative rate is as low as 0.4&#x0025;. Therefore, the proposed algorithm has considerable potential practical application.

Quadrature Cosine Transform (QCT) With Varying Window Length (VWL) Technique for Noncontact Vital Sign Monitoring Using a Continuous-Wave (CW) Radar

For noncontact vital sign monitoring by using a continuous-wave (CW) radar, the quadrature cosine transform (QCT) with varying window length (VWL) technique is proposed in this article for the first time. The novel algorithm can directly yield the vibration frequency of the radar’s output <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IQ</i> signals with multiple advantages, including the elimination of dc offset calibration and mitigation of nonlinear interferences caused by harmonic and intermodulation terms, and there is a 50% reduction in frequency resolution of the conventional Fourier transform (FT) that is commonly utilized in existing articles. Thus, it can strike a balance between accuracy and computational efficiency with a short window length. The excellent performance was demonstrated by both theoretical predictions and simulation results. Experiments involving a participant seated 1 m away from the 2.4-GHz ISM band radar prototype demonstrated that the proposed algorithm measures the respiratory rate variability (RRV) and short-time heart rate (HR) with respective errors of less than 1% and 3%. Moreover, the proposed algorithm was more accurate than conventional methods with various window lengths (3–27 s) in 10-min noncontact experiments to monitor the vital signs of ten participants.

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.

A loop-unrolled assisted 9b 700 MS/s nonbinary 2b/cycle SAR ADC with time-based offset calibration

This paper presents a nonbinary 2b/cycle SAR ADC structure with two assistant loop-unrolled comparators. By using the reset time of 2-bit comparators, the proposed structure achieves extra single bit conversion after normal 2-bit conversions, thus removing one comparison period compared with conventional 2-bit SAR. A nonbinary decision scheme is realized to relax the DAC voltage settling requirement, especially the signal-DAC voltage for loop-unrolled conversion. Besides, a low kick back noise comparator is adopted with time-based offset calibration, which reduces DAC voltage fluctuation and eliminate offset mismatch. Simulation result shows that the ADC achieves 53.35 dB SNDR at Nyquist input frequency after offset calibration, resulting in a Walden FoM of 28.76fJ/conversion-step.

Analysis of strong-arm comparator with auxiliary pair for offset calibration

This paper analyzes the principle of the input-referred off calibration using the auxiliary pair for Strong-Arm comparator as well as its impact from the additional common-mode current and parasitic capacitance on the input-referred noise, offset, and decision time in detail. The comparison with the simulation results demonstrates the accurate prediction with the proposed analysis. This paper also discusses the design guideline to optimize the Strong-Arm comparator with the auxiliary pair for offset calibration.

An offset calibration technique for CIS column-parallel SAR ADCs using memory

A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of &#xC2;&#xB1;32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

Automatic calculation of the magnetometer zero offset using the interplanetary magnetic field based on the Wang–Pan method

The space-borne fluxgate magnetometer (FGM) requires regular in-flight calibration to obtain its zero offset. Recently, Wang GQ and Pan ZH (2021a) developed a new method for the zero offset calibration based on the properties of Alfvén waves. They found that an optimal offset line (OOL) exists in the offset cube for a pure Alfvén wave and that the zero offset can be determined by the intersection of at least two nonparallel OOLs. Because no pure Alfvén waves exist in the interplanetary magnetic field, calculation of the zero offset relies on the selection of highly Alfvénic fluctuation events. Here, we propose an automatic procedure to find highly Alfvénic fluctuations in the solar wind and calculate the zero offset. This procedure includes three parts: (1) selecting potential Alfvénic fluctuation events, (2) obtaining the OOL, and (3) determining the zero offset. We tested our automatic procedure by applying it to the magnetic field data measured by the FGM onboard the Venus Express. The tests revealed that our automatic procedure was able to achieve results as good as those determined by the Davis–Smith method. One advantage of our procedure is that the selection criteria and the process for selecting the highly Alfvénic fluctuation events are simpler. Our automatic procedure could also be applied to find fluctuation events for the Davis–Smith method.

Low-Noise Resistive Bridge Sensor Analog Front-End Using Chopper-Stabilized Multipath Current Feedback Instrumentation Amplifier and Automatic Offset Cancellation Loop

Resistive bridge sensors are used in many application areas to measure changes in physical parameters. To amplify the resistive changes from sensing elements with high precision, various offset contributors in the resistive bridge and amplifiers should be minimized. This study proposes a low-noise resistive bridge sensor analog front-end (AFE) using a chopper-stabilized multipath current feedback instrumentation amplifier (CFIA) and an automatic offset cancellation loop. The proposed circuit exploits a multipath chopper-stabilized architecture for obtaining low noise performance and wide bandwidth characteristics. This circuit can minimize the offsets in the bridge and the high frequency and low frequency amplifiers, while achieving high precision resistive signal acquisition. The high frequency path of the multipath amplifier uses the CFIA topology with class-AB output stage. The offset in the high frequency path is stabilized by the low frequency path amplifier with a high gain and low noise chopper amplifier. The up-modulated offset in the low frequency chopper amplifier path is reduced by the AC-coupled ripple reduction loop (RRL). An automatic offset calibration loop (AOCL) circuit was designed to calibrate the offset due to the bridge mismatch. The AOCL reduces the bridge offset using a successive approximation register (SAR)-based binary-search algorithm. The gain of the proposed circuit is adjustable from 15.56 dB to 44.14 dB. The AFE is implemented in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~ \boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> CMOS process and draws <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$123~ \boldsymbol {\mu } \text{A}$ </tex-math></inline-formula> current from a 3.3 V supply. The input referred noise and noise efficiency factor (NEF) are 14.6 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\surd } $ </tex-math></inline-formula> Hz and 6.1, respectively.

Unified Parameterization and Calibration of Serial, Parallel, and Hybrid Manipulators

In this work, we present methods allowing parallel, hybrid, and serial manipulators to be analyzed, calibrated, and controlled with the same analytical tools. We introduce a general approach to describe any robotic manipulator using established serial-link representations. We use this framework to generate analytical kinematic and calibration Jacobians for general manipulator constructions using null space constraints and extend the methods to hybrid manipulator types with complex geometry. We leverage the analytical Jacobians to develop detailed expressions for post-calibration pose uncertainties that are applied to describe the relationship between data set size and post-calibration uncertainty. We demonstrate the calibration of a hybrid manipulator assembled from high precision calibrated industrial components resulting in 91.1 μm RMS position error and 71.2 μrad RMS rotation error, representing a 46.7% reduction compared to the baseline calibration of assembly offsets.

An Iterative-Optimization-Based Calibration Framework for VIO With Limited Prior Conditions

Most of the visual inertial positioning accuracy is constrained by the calibration accuracy of the sensor, however, there are few navigation systems that take the time offset and extrinsic parameters into account at the same time. In this paper, an iterative-optimization-based calibration framework for VIO (visual-inertial odometry) with limited prior conditions is proposed. In particular, a three-stage calibration method is presented, which includes the time offset estimation stage, the extrinsic and intrinsic parameters calibration stage, and global temporal and IMU parameter optimization stage. In the first stage, the time offset calibration model is proposed, which estimates the time delay by iteratively optimizing the orientation residual equation. In the second stage, based on the assumption of constant angle velocity and linear velocity between two continuous keyframes, an iterative-based coarse-to-fine calibration strategy is presented to calibrate the initial extrinsic and IMU intrinsic parameters. In the third stage, a global optimization-based algorithm is introduced to obtain a more accurate time offset value and IMU intrinsic parameters. What’s more worth mentioning is that the proposed method does not require any prior parameters, which greatly improves the universality of the navigation system. To evaluate the effectiveness and accuracy of the proposed algorithm, the method is tested on both simulation and public dataset, and also compared with classical systems. Abundant experimental results illustrate that the proposed method can effectively estimate the time offset, the IMU intrinsic and extrinsic parameters.