Abstract
This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.
Highlights
Ultra-high sample rate analog-to-digital converters (ADCs) operating at several tens of gigahertz are increasingly demanded in leading-edge instruments, optical communications, multiple-input multiple-output (MIMO) systems, and 6G communications [1,2,3,4,5,6]
Previous studies show that single-channel successive approximation register (SAR) ADC are suited for the designs that operate at around 1 GS/s with 6–8b resolution [7,8,9,10]
Kull et al implemented a 24–72 GS/s 8 bit TI-SAR ADC with on chip gain and time-skew calibration, where their coefficients were obtained by off-line calculation utilizing the stored data in the memory [18]
Summary
Ultra-high sample rate analog-to-digital converters (ADCs) operating at several tens of gigahertz are increasingly demanded in leading-edge instruments, optical communications, multiple-input multiple-output (MIMO) systems, and 6G communications [1,2,3,4,5,6]. K. Sun et al designed a 56 GS/s 8 bit TI-SAR ADC with foreground calibration employing an off-line algorithm to calculate the coefficients for the offset, gain, and time skew [19]. Sun et al designed a 56 GS/s 8 bit TI-SAR ADC with foreground calibration employing an off-line algorithm to calculate the coefficients for the offset, gain, and time skew [19] These designs mainly focus on the ADC core with on-chip memory and partial data output, which cannot achieve high calibration accuracy and implement realtime data output. For real-time data output, deterministic latency plays a vital role to implement precise data collection and multi-chip synchronization To address these issues, this paper presents a 56 GS/s 8 bit time-interleaved ADC with 16-lane 28 Gb/s transmitters. This paper is structured as follows: Section 2 describes the chip architecture; Section 3 explains the ADC implementation; Section 4 presents the ADC calibration algorithm; Section 5 introduces the deterministic latency and synchronization in detail; Section 6 shows the measured results; and Section 7 draws the conclusion
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