Offset Calibration Technique Research Articles

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register analogue‐to‐digital converter using offset‐mismatch calibrated comparators

AbstractThis letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage.

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

An offset calibration technique for CIS column-parallel SAR ADCs using memory

A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of &#xC2;&#xB1;32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.

A statistical offset calibration technique for 1.5-bit/cycle SAR ADCs

This paper presents a statistical offset calibration technique for 1.5-bit/cycle successive approximation register (SAR) analog-to-digital converters (ADCs). It estimates the offset polarity by comparing the number of 0 and 1 in specific conversion cycles and performs compensation in the analog domain. Compared to prior works based on zero input injection, the proposed method avoids the metastability issue which influences the calibration accuracy and convergence. As a proof of concept, an 8-bit 350-MS/s SAR ADC with 1.5-bit/cycle operation and offset calibration is fabricated in 65-nm CMOS. Measurement results show that after offset calibration, the SNDR and SFDR are improved by 5.6 dB and 5.9 dB, respectively. The active area of the calibration circuit is 0.01 mm2.

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\times$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

A 6-bit 2.5-GS/s $8\times $ dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high-speed applications. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time domain with an interpolation factor of 8, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The sequential slope-matching offset calibration scheme is proposed not only for VTC offset but also for interpolated ZX accuracy. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65-nm CMOS process and occupies a 0.12 mm2 chip area, including offset calibration circuitry. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration are 0.68 and 0.65 LSB, respectively. With a 1.23 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 33.84 and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype ADC achieves a figure of merit (FoM) of 74.7 fJ/conversion step at 2.5 GS/s.

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analog-to-digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage $V_\mathrm{cm}$ . To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective $V_\mathrm{cm}$ - adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noise-plus-distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

10 Mbps 0.3 nJ/bit OQPSK transceiver IC for 400–450 MHz medical telemetry

A 10 Mbps OQPSK transceiver working in the 400–450 MHz frequency range is designed for medical telemetry applications requiring wireless communication with both high data rate and low power consumption. An inverter based phase-switching transmitter has been proposed to lower the transmitter power consumption. Moreover, a digital-assisted DC offset calibration (DCOC) technique that combines the PGA-gain-uncorrelated DCOC method and a lookup table is adopted to enable an zero-IF receiver architecture. Fabricated in 65 nm CMOS process, both the transmitter and the receiver consumes ∼3 mW from 1 V supply at 10 Mbps data rate. The transceiver energy efficiency is ∼0.3 nJ/bit, which outperforms the similar designs in recent literature.

Offset calibration technique for capacitive transimpedance amplifier used in uncooled infrared detection

This paper presents a novel readout circuit of uncooled, bolometer-based, focal plane arrays (FPAs). The offset and flicker noise are the design challenges of microbolometer readout circuits (ROCs). The ROC is not only required to apply careful noise cancellation techniques, but also to be insensitive to process and supply voltage variations. The proposed circuit involves a new offset cancellation technique which overcomes process variations, noise, random, and systematic offset.

A precision comparator design with a new foreground offset calibration technique

This paper presents a new digitally-assisted analog foreground comparator offset calibration technique that is fast, compact, low-power, precise, and linear. Non-linear input referred DC offset voltage of a comparator used in an analog-to-digital converter (ADC) is considered as the most important factor that degrades performance, especially for ADC architectures that utilize multiple comparators, such as flash ADCs. This paper discusses the causes of various types of offsets as well as techniques for cancelling them in dynamic latched comparators. Both background and foreground offset calibration techniques used in dynamic comparators are explained. Three popular circuit implementation approaches for foreground calibration are reviewed. A novel coarse---fine calibration (CFC) technique is introduced presenting concept of operation and its effectiveness over other available analog foreground offset calibration techniques. Simulation and measurement results of dynamic comparators that were fabricated in 2P3M, 3.3 V, 0.35 μm CMOS process are presented. It was shown that the proposed CFC technique achieves better performance than other digitally-assisted analog calibration techniques without requiring high-resolution (>8-bit) trimming digital-to-analog converters while providing compact, high-speed, low-power, and linear offset correction over the full offset range of up to ±100 mV.

분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of is fabricated using a 0.18- CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

A 6bit, 7mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

SUMMARY A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator’s offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique

The current accuracy and power efficiency of a boost white light-emitting-diode (WLED) driver are usually design tradeoffs since the power efficiency is inversely proportional to the reference voltage, whereas the current accuracy is proportional to the reference voltage. Traditionally, a boost WLED driver with high current accuracy and high power efficiency demand a large chip area because mismatch decreases with increasing size. This paper proposes an offset calibration technique to improve both current accuracy and power efficiency while keeping the chip area relatively small. An overvoltage protection (OVP) circuit and an overcurrent protection (OCP) circuit prevent the proposed driver from being damaged due to WLED failure. The design is fabricated in a Taiwan Semiconductor Manufacturing Company 0.25-μm 60-V bipolar-CMOS-double-diffused-MOS process. The measurement results show that the current variation is less than 1% when the input voltage and the number of loaded WLEDs are varied in a wide range. The maximum power conversion efficiency is 86.7% at a 5-V input with four loaded WLEDs. The OVP is 58 V, and the OCP is 2 A.

Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs

A bulk voltage trimming offset calibration technique is presented for flash analog-to-digital converters (ADCs). Offset calibration is achieved by digitally adjusting the bulk voltages of the preamplifier input devices. Without introducing additional capacitive loading in the analog path, this technique improves the accuracy of flash ADCs while not impairing their high-speed performance. A 4-bit ADC in 90-nm CMOS with the proposed technique achieves 3.71 effective number of bits (ENOB) at 5-GS/s sampling rate with 2.5-GHz effective resolution bandwidth (ERBW). The calibration generally improves ENOB by approximately 0.5 bit after calibration. The ADC consumes 86 mW at 5 GS/s with a 2.5-GHz input achieving a 1.32-pJ/convstep figure of merit. The ADC occupies 0.135-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area.