Off-state Stress Research Articles

Analysis of degradation mechanism in polycrystalline silicon thin-film transistors under dynamic off-state stress with fast transition time

Abstract This study represents the investigation into the degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dynamic off-state stress, with a focus on transition times as rapid as 1 nanosecond (ns). The study found that dynamic off-state stress with larger amplitude leads to more severe device degradation. Unlike previous studies, both the rising time (t r ) and falling time (t f ) of the pulse significantly influence the hot carrier (HC) degradation in the poly-Si TFTs. The on-state current degradation rate (ΔI on ) after 104 s stress dramatically increases from 11.8% to 80.8% when t r decreases from 500 ns to 1 ns. When t f decreases from 500 ns to 1 ns, ΔI on also dramatically increases from 22.9% to 69.2%. Combined with transient simulations, the source of the carrier for HC degradation is clarified and consequently, a non-equilibrium PN junction degradation model modulated by accumulated electrons is developed.

Recovery of drain-induced threshold voltage shift by positive gate bias in GaN power HEMTs with p-GaN gate

We demonstrate that exposure to positive gate bias can favor a fast recovery of the threshold voltage variation induced by off-state stress, in p-GaN gate high electron mobility transistors. Two process splits were investigated, having different Schottky barriers at the metal/p-GaN junction. Results indicate that: (a) drain stress may result in significant threshold voltage increase; (b) devices with sufficiently high gate leakage current show an immediate recovery after gate turn-on, resulting in stable operation in actual applications. The contribution of leakage current is demonstrated, based on recovery experiments at different voltages and for the same rate of hole injection from the gate.

Rapid detection of capture and emission processes in surface and buffer traps: Understanding dynamic degradation in GaN power devices

This study utilized a rapid detection technique, Isothermal Capture Transient Spectroscopy (ICTS), to identify and evaluate defects related to GaN device surface and buffer traps, and investigated the mechanisms by which they affect the dynamic performance of GaN based devices. Interface states and dielectric bulk traps were analyzed, unveiling distinctive device behavior under positive gate pulse-biased ICTS. The observed S-shaped threshold voltage (VTH) instability and dynamic gate-drain capacitance (CGD) issues were directly associated with these interface states and bulk traps. Negative gate pulse-biased ICTS revealed the presence of logarithmic electron trapping originating from extended electron traps, and spatial wide distributed hole traps within the GaN buffer layer, significantly impacting the dynamic on-resistance (RON) during off-state stress of the devices. The rapid assessment capabilities of this method provide a valuable tool for optimizing GaN epitaxy and manufacturing processes.

Degradation Mechanisms of Hydrogen-Terminated Diamond MISFETs Under Off-State Stress Conditions

Degradation Mechanisms of Hydrogen-Terminated Diamond MISFETs Under Off-State Stress Conditions

Low temperature recovery of OFF-state stress induced degradation of AlGaN/GaN high electron mobility transistors

Thermal annealing is a widely used strategy to enhance semiconductor device performance. However, the process is complex for multi-material multi-layered semiconductor devices, where thermoelastic stresses from lattice constant and thermal expansion coefficient mismatch may create more defects than those annealed. We propose an alternate low temperature annealing technique, which utilizes the electron wind force (EWF) induced by small duty cycle high density pulsed current. To demonstrate its effectiveness, we intentionally degrade AlGaN/GaN high electron mobility transistors (HEMTs) with accelerated OFF-state stressing to increase ON-resistance ∼182.08% and reduce drain saturation current ∼85.82% of pristine condition at a gate voltage of 0 V. We then performed the EWF annealing to recover the corresponding values back to ∼122.21% and ∼93.10%, respectively. The peak transconductance, degraded to ∼76.58% of pristine at the drain voltage of 3 V, was also recovered back to ∼92.38%. This recovery of previously degraded transport properties is attributed to approximately 80% recovery of carrier mobility, which occurs during EWF annealing. We performed synchrotron differential aperture x-ray microscopy measurements to correlate these annealing effects with the lattice structural changes. We found a reduction of lattice plane spacing of (001) planes and stress within the GaN layer under the gate region after EWF annealing, suggesting a corresponding decrease in defect density. Application of this low-temperature annealing technique for in-operando recovery of degraded electronic devices is discussed.

Trade-off between gate leakage current and threshold voltage stability in power HEMTs during ON-state and OFF-state stress

We present a detailed investigation of the impact of electron gate leakage on the threshold voltage stability of normally-off GaN HEMTs with p-GaN gate. The analysis is based on combined DC, pulsed and transient measurements, carried out on two test wafers with different gate processes, resulting in different levels of gate leakage current. The key results demonstrate: (a) the existence of four different charge-trapping processes, whose interplay determines the sign and amplitude of the threshold voltage variation; (b) a reasonable increase in gate leakage is beneficial for eliminating the negative threshold voltage instability under positive gate bias, and for substantially reducing the positive threshold shift under off-state stress. Furthermore, (c) we present a proper characterization methodology for device understanding.

Adaptive Level-Shift Gate Driver With Indirect Gate Oxide Health Monitoring for Suppressing Crosstalk of SiC MOSFETs

An adaptive level-shift gate driver with indirect gate oxide health monitoring for suppressing crosstalk of bridge-leg configured SiC MOSFETs is proposed. This paper firstly presents a holistic assessment of the changes in major intrinsic parameters before and after aging SiC MOSFETs with repetitive short-circuit tests. Gate leakage is found to be an appropriate precursor to reflect gate oxide degradation. Then, the structure, operation, and design of the proposed gate driver are given. The working principle is based on using a digitally controlled variable resistor in a resistor-capacitor-based voltage divider network to adjust the off-state gate-source voltage. Then, the peak off-state gate-source voltage caused by the spurious voltage is regulated at a level that can avoid shoot-through and reduce off-state voltage stress on the gate. Besides suppressing crosstalk, an optimal off-state gate-source voltage can also improve the life expectancy of SiC MOSFET. By utilizing the loading effect of gate leakage current on the proposed gate driver output, the gate oxide degradation is indirectly monitored by observing the change in the value of the variable resistor. The proposed gate driver has been evaluated on a 1kW inverter prototype under various intrinsic parameter variations. Performance comparisons between proposed and traditional gate drivers are given.

Investigation of Off-State Stress Induced Degradation of SiC MOSFETs Under Short-Circuit Condition

Investigation of SiC MOSFETs short-circuit (SC) degradation mechanism is critical to improve the overall reliability of power converters. At present, research on the SiC MOSFETs degradation mechanism mainly focuses on the on-state phase of the SC period. While, ruggedness of SiC MOSFETs in the off-state phase of short-circuit tests (SCTs) were neglected. In this paper, SiC MOSFETs degradation mechanism in the off-state phase of SCTs are investigated comprehensively. Specifically, distribution and magnitude of electrothermal stress of devices under test (DUTs) in the off-state phase of SCTs are analyzed by TCAD simulation. Which reveals two important phenomena: i) the device will suffer from long-term high temperature and high electric field stress in the off-state phase when negative turn-off gate voltage (Vgs-off) is applied; ii) high hole current in the channel region will last for several microseconds after the device is turned off. The observed SiC MOSFETs degradation in the off-state phase of SCTs is then proved by experiments, through which, the excessively low Vgs-off can reduce the SC capability of SiC MOSFETs is concluded. Moreover, the degradation results of static parameters of SiC MOSFETs are presented and the degradation mechanism is analyzed in detail.

Recovery of off-state stress-induced damage in FET-type gas sensor using self-curing method

The need for high-performance gas sensors is driven by concerns over indoor and outdoor air quality, and industrial gas leaks. Due to their structural diversity, vast surface area, and geometric tunability, metal oxides show significant potential for the development of gas sensing systems. Despite the fact that several previous reports have successfully acquired a suitable response to various types of target gases, it remains difficult to maintain the reliability of metal oxide-based gas sensors. In particular, the degradation of the sensor platform under repetitive operation, such as off-state stress (OSS) causes significant reliability issues. We investigate the impact of OSS on the gas sensing performances, including response, low-frequency noise, and signal-to-noise ratio of horizontal floating-gate field-effect-transistor (FET)-type gas sensors. The 1/f noise is increased after the OSS is applied to the sensor because the gate oxide is damaged by hot holes. Therefore, the SNR of the sensor is degraded by the OSS. We applied a self-curing method based on a PN-junction forward current at the body–drain junction to repair the damaged gate oxide and improve the reliability of the sensor. It has been demonstrated that the SNR degradation caused by the OSS can be successfully recovered by the self-curing method.

Impact of OFF-State, HCI and BTI degradation in FDSOI Ω-gate NW-FETs

In this work, the degradation of N-type FDSOI Ω-gate NW-FETs caused by OFF-State stress under different conditions has been experimentally studied and compared with the effects of positive/negative BTI and HCI aging. The experimental observations show that, in these devices, HCI and OFF-State are the most damaging aging mechanisms while N/PBTI stresses produce negligible degradation. Moreover, for large enough stress conditions, OFF-State aging introduces large leakage currents, largely distorting the ID-VG curves of the transistor.

Unique Role of Hot-Electron Induced Self-Heating in Determining Gate-Stack Dependent Dynamic R ON of AlGaN/GaN HEMTs Under Semi-on State

In this work, we report a unique dependence of dynamic RON on gate-stack of AlGaN/GaN high electron mobility transistors (HEMTs) on carbon (C)-doped GaN buffer under semi-on condition. Unlike the OFF-state stress, semi- ON state stressing of the devices revealed a significantly lower dynamic RON in the Schottky HEMTs when compared to SiNx-gated HEMTs. Detailed experiments including substrate bias dependence, electro-luminescence (EL) spectrum, and electric field analysis established electron trapping in the GaN buffer to be the source of dynamic RON in both the HEMT types. An on-the-fly thermal analysis, using thermoreflectance technique, revealed Schottky HEMTs to have a higher hot electron-induced self-heating near the field plate (FP) edge as compared to SiNx-gated devices. The higher lattice temperature was found to result in a significantly higher electron de-trapping from the buffer traps. The higher de-trapping reduced the dynamic RON in the Schottky HEMTs as compared the SiNx-gated devices.

Degradation induced by holes in Si3N4/AlGaN/GaN MIS HEMTs under off-state stress with UV light

Degradation induced by holes in Si3N4/AlGaN/GaN MIS HEMTs under off-state stress with UV light

Cumulative Hot-Electron Trapping in GaN-Based Power HEMTs Observed by an Ultrafast (10 V/Ns) On-Wafer Methodology

The goal of this article is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based high electron mobility transistors (HEMTs). To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W_{G}=2$ </tex-math></inline-formula> mm p-type GaN HEMTs with different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm {ON}}$ </tex-math></inline-formula> compared with OFF-state stress. Third, by comparing the results on identical devices having shorter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> , we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer), we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.

Identification of Traps in p-GaN Gate HEMTs During OFF-State Stress by Current Transient Method

In this work, the current transient method was conducted for trap analysis in the p-GaN gate high-electron-mobility transistors (HEMTs) in the OFF-state. Based on the traditional detrapping transient measurements, the pure recovery transients can be isolated by subtracting the undetected part caused by the measurement conditions. A comparison of the measured and actual recovery transients under different drain filling voltages was presented. It suggested that this method can be effective to analyze the unregular transient curves and distinguish the charge trapping type preliminarily. In addition, three traps were identified based on the time constant spectra and the hidden absolute amplitudes of traps can be corrected using the differential amplitude spectra. The information of trap levels in the buffer layer and AlGaN barrier layer was revealed, consisting of three electron traps with energy levels of 0.313, 0.265, and 0.467 eV. The identification of the traps may provide a physical foundation for better understanding of the drain-induced trapping effect during the OFF-state in p-GaN HEMTs.

Fluorine-plasma treated AlGaN/GaN high electronic mobility transistors under off-state overdrive stress

Influences of off-state overdrive stress on the fluorine-plasma treated AlGaN/GaN high-electronic mobility transistors (HEMTs) are experimentally investigated. It is observed that the reverse leakage current between the gate and source decreases after the off-state stress, whereas the current between the gate and drain increases. By analyzing those changes of the reverse currents based on the Frenkel–Poole model, we realize that the ionization of fluorine ions occurs during the off-state stress. Furthermore, threshold voltage degradation is also observed after the off-state stress, but the degradations of AlGaN/GaN HEMTs treated with different F-plasma RF powers are different. By comparing the differences between those devices, we find that the F-ions incorporated in the GaN buffer layer play an important role in averting degradation. Lastly, suggestions to obtain a more stable fluorine-plasma treated AlGaN/GaN HEMT are put forwarded.

Method to Distinguish Between Buffer and Surface Trapping in Stressed Normally-ON GaN GITs Using the Gate-Voltage Dependence of Recovery Time Constants

Drain current recovery transients are analyzed in normally-ON (NON) gate injection transistors (GITs) subjected to different kinds of stress. The recovery is measured as a function of forward gate bias, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> , which controls the number of holes injected from the gate and speeds up the recovery. Unlike conventional normally-OFF GITs, the newly designed NON GIT test structures allow simple characterization of buffer trapping during back-gating. By comparing the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> -dependence of recovery time constants for OFF-state and semi- ON state stress with those obtained from back-gating experiments we are able to distinguish between buffer and surface trapping. Our approach is simple and does not require time-consuming temperature-dependent measurements. It is found that OFF-state stress causes negative charge accumulation in the buffer, while semi- ON state stress leads to accumulation in both, buffer and surface. The use of NON GITs enables to measure the recovery time constants related to the buffer over a wide span of six orders of magnitude ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-{4}}$ </tex-math></inline-formula> –100 s).

Demonstration of Schottky barrier diode integrated in 200 V power p-GaN HEMTs technology with robust stability

Development of integration of different components with GaN-based technologies has been gaining traction in recently. Among these, diodes play important roles in GaN power ICs. For this work, a fabrication approach for integrating a Schottky barrier diode (SBD) with a p-GaN enhancement (E-mode) for 200 V switching application is demonstrated. The integrated SBD with 30-mm width shows a low forward voltage (Vf) with more than 10A and 6A at Vac = 3 V at 25 °C and 150 °C, respectively. Additionally, the devices show a stable ON-resistance (RON) (<20% increase) up to 200 V at 25 °C/150 °C under pulsed IV characterization and OFF-state stress, pointing out the robust stability for integrated GET-SBDs on a power p-GaN HEMT platform.

Comparison of OFF-State, HCI and BTI degradation in FDSOI Ω-gate NW-FETs

In this work, the degradation of N-type FDSOI Ω-gate NW-FETs caused by OFF-State stress under different conditions has been experimentally studied and compared with the effects of positive/negative BTI and HCI aging. The experimental observations show that HCI and OFF-State are the most damaging aging mechanisms in these devices while N/PBTI produce negligible degradation. Moreover, for large enough stress conditions, OFF-State aging largely distorts the ID-VG curves of the transistor, leading to an almost linear dependence on VG.

High-Temperature Static and Dynamic Characteristics of 4.2-kV GaN Super-Heterojunction p-n Diodes

This article presents the static and dynamic characterization of 4.2-kV super-junction p-n diodes at high temperatures. Reduction of the forward current with increasing temperature is consistent with 2DEG mobility degradation caused by polar optical phonon scattering. Reverse leakage current was dominated by isolation leakage, with an activation energy of ~0.26 eV, close to the reported activation energy of surface leakage. Dynamic switching characterization in the temperature range from room temperature (RT) to 300 °C showed a nonmonotonic dependence of dynamic ON-resistance on temperature. At room temperature and 50 °C, devices showed zero current collapse (CC) up to OFF-state stress bias of 3 kV at 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> timescale. Between 100 °C and 200 °C, significant CC was observed. From 250 °C to 300 °C, devices showed recovery from the severe CC. The degradation and recovery of dynamic ON-resistance can be explained by emission and recapture of holes during the OFF- and ON-states, respectively.

Investigating two-stage degradation of threshold voltage induced by off-state stress in AlGaN/GaN HEMTs

In this work, a two-step degradation phenomenon in D-mode Si3N4/AlGaN/GaN metal–insulator–semiconductor-high electron mobility transistors is discussed systematically. During off-state stress, threshold voltage shifts positively for a short duration, and is followed by a negative shift. In contrast, the off-state leakage continues to decrease throughout the entire stress. Results of varied measurement conditions indicate that carrier trapping at different regions dominates this phenomenon. It is interesting that under a large lateral electric field, electron–hole pairs are generated and will then be trapped at the gate dielectric layer. Furthermore, when increasing the stress temperature, impact ionization due to carriers from the gate electrode becomes more severe. Finally, devices with different gate insulator thicknesses are performed to verify the physical model of the degradation behavior.