Cumulative Hot-Electron Trapping in GaN-Based Power HEMTs Observed by an Ultrafast (10 V/Ns) On-Wafer Methodology

Abstract

The goal of this article is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based high electron mobility transistors (HEMTs). To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W_{G}=2$ </tex-math></inline-formula> mm p-type GaN HEMTs with different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\mathrm {ON}}$ </tex-math></inline-formula> compared with OFF-state stress. Third, by comparing the results on identical devices having shorter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L_{\text {GD}}$ </tex-math></inline-formula> , we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer), we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.