Off-state Drain Bias Research Articles

Investigation of the Trapping and Detrapping Behavior by the On-State Resistance at Low Off-State Drain Bias in Schottky p-GaN Gate HEMTs

GaN power HEMTs enable the design of power electronic systems with highest efficiencies and reduced size. Despite strong advancements in device reliability, charge carrier trapping is still an important challenge. The applied methodology allows to characterize defects that cause the dynamic RDS,on in GaN power devices at product level with flexibility in duty cycle, number of pulses and mission profile. A pronounced trapping is observed for lateral GaN-on-Si HEMTs with Schottky p-GaN gate structure at low drain bias and long off-state pulses (> 100 ms). The effect is investigated by fast determination of the on-state resistance RDS,on under different trap capturing conditions: a) different drain bias b) off-state time and number of cycles c) variation of temperature. The trapping and detrapping effects are characterized and the activation energy is extracted from time constants. An elevated on-state resistance was present for up to 3 hours. The threshold voltage modification due to high drain bias does explain the significant RDS,on increase.

Vertical field inhomogeneity associated with threading dislocations in GaN high electron mobility transistor epitaxial stacks

A measurement technique combining Kelvin-probe force microscopy with substrate bias is developed and demonstrated on AlGaN/GaN-on-Si device structures under conditions relevant to the effect of off-state drain bias stress in transistors. For a high substrate bias, the measurements show a significantly lowered surface potential surrounding a small proportion of dislocations imaged with atomic force microscopy (AFM), laterally extending on a scale of up to a micrometer. Both the density and the size of those features increase with substrate bias; however, conductive AFM measurements under the same bias conditions showed no leakage reaching the surface associated with those features. Our model considers localized conductive paths that end a certain distance below the 2D electron gas electrically “thinning” the epitaxy and, therefore, deforming the potential and increasing the electric field under off-state stress bias. The conclusion is that the vertical electric field in the buffer is laterally highly non-uniform with an enhanced vertical field in the vicinity of those dislocations. This non-uniformity redirects the substrate bias stress from the buffer to the channel with potential consequences for breakdown.

Characterization of Dynamic Threshold Voltage in Schottky-Type p-GaN Gate HEMT Under High-Frequency Switching

The dynamics of the intrinsic threshold voltage ( ${V}_{{\text {TH}}}{)}$ shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching is investigated by a bootstrap voltage clamping circuit in which the GaN HEMT serves as the key bootstrapping device. This new testing setup covers a wide range of OFF-state drain bias ( ${V}_{{\text {DSQ}}}{)}$ up to 400V, a short OFF-to-ON (or stress-to-sense) delay ( ${T}_{{\text {delay}}}{)}$ of 60ns, and a high switching frequency ( ${f}_{{\text {sw}}}{)}$ up to 2MHz. The dynamic ${V}_{{\text {TH}}}$ ’s dependences on ${V}_{{\text {DSQ}}}$ and ${f}_{{\text {sw}}}$ are characterized by this testing setup. A higher VDSQ (up to 400V) results in a larger dynamic ${V}_{{\text {TH}}}$ shift ( $\Delta {V}_{{\text {TH}}}{)}$ . The $\Delta {V}_{{\text {TH}}}$ exhibits a gradually increasing trend under the continuous high-frequency switching mode. In addition, after continuous switching operation for $200\mu \text{s}$ , the maximum $\Delta {V}_{{\text {TH}}}$ shows no ${f}_{{\text {sw}}}$ dependence with a wide range of frequency from 50kHz to 2MHz.

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

In this paper, input capacitance (CISS) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. CISS includes gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD). In comparison with the normally-on HEMTs, it is found that the phenomenon of CISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of CISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of CGS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing CGS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of CGD. Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on CISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the CISS related capacitance design and gate driver optimization of the devices.

Vertical GaN n-channel MISFETs on ammonothermal GaN substrate: Temperature dependent dynamic switching characteristics

Switching of GaN-based vertical-trench gate MISFET on ammonothermal n-type GaN substrate are studied as a function of temperature. Pulsed on-state IV characterization revealed three unexpected independent effects. First, drain current increases with temperature, although electron mobility decreases with temperature. Second, drain current decreases with pulse length, which cannot be explained by heating. Third, dynamic Ron increases with off-state drain bias, which usually is considered as an issue of lateral GaN HFETs only. The drain current temperature dependence is most likely dominated by the low electron mobility in the inversion layer beneath the gate. The field effect channel mobility is estimated as < 10 cm2/V s and can thus be considered as trap limited and thermally activated, Ron decreases from 133 Ω mm at 20 °C to 62 Ω mm at 110 °C. Longer on-state pulses lead to negative charging of the ALD-Al2O3 gate oxide and shift the threshold voltage (DC-Vth ~8 V) positively. With the maximum applicable Vgs = 10 V, the drain current is not saturated yet and Ids thus drops by a factor 2 when increasing the on-state pulse width from 0.2 µs to 20 µs due to the Vth-shift. The observed 10-times dynamic Ron increase with off-state drain bias up to 30 V can be related to possible charging mechanism in the gate oxide as well. Activation energies for different off-state stress voltage are ranged linear between 0.08 eV and 0.26 eV for drain bias stress of Vds = 0 V and 30 V respectively.

Reliability Improvement of GaN Devices on Free-Standing GaN Substrates

In order to analyze the influence of different substrates on the performance of metal–insulator–semiconductor AlGaN/GaN high-electron mobility transistors, devices on free-standing GaN (FS-GaN), silicon, and sapphire substrates with similar AlGaN/GaN top layers were fabricated. Compared with Si and sapphire substrates, the devices on the FS-GaN substrate not only achieve remarkable improvement in the direct current characteristics but also have much better thermal stability and can significantly suppress the self-heating effects, where the current density only decreases by 4% with the channel at 48 °C and an ambient of 25 °C. Owing to the lower trap and dislocation densities in the epitaxial layers, the dynamic performance and reliability of the devices on the FS-GaN substrate are also dramatically improved. With an off-state drain bias of 50 V kept for 10 s, the devices on the FS-GaN substrate only suffer a 10% increase in dynamic on resistance, much lower than the devices on the Si and sapphire substrates. In addition, all the devices were exposed to a 3-MeV proton irradiation with a dose of $\text {3} \times \text {10}^{\text {14}}$ cm−2. Compared with the devices before radiation treatment, the dynamic on resistance increases by 79% with a 20-V off-state stress for the devices on the FS-GaN substrate, while the increase is over 800% for the other devices. The lower performance degradation for the devices on the FS-GaN substrate indicates a lower displacement damage and better irradiation tolerance.

On the origin of dynamic Ron in commercial GaN-on-Si HEMTs

There are huge differences in dynamic on-resistance Ron, also known as current-collapse, between current GaN power HEMT technologies. Here we illustrate this fact with dynamic Ron measurements on two commercially available devices from 2 different manufacturers, with one showing more than a factor of 2 increase in dynamic Ron after OFF-state drain bias (type 1) and the other one <15% change. HTRB stress for 1000h and 3000h on type 1 and type 2 respectively was found to only make subtle changes to dynamic Ron, with type 1 still showing a much larger dynamic Ron than type 2. A model for dynamic Ron is presented based on a floating, highly resistive, epitaxial buffer whose potential is determined by parasitic leakage paths. The difficulty in controlling local leakage paths can explain the problems that manufacturers are still finding in suppressing dynamic Ron.

Performance Improvement and Current Collapse Suppression of Al2O3/AlGaN/GaN HEMTs Achieved by Fluorinated Graphene Passivation

In this letter, fluorinated graphene (FG) is utilized to passivate GaN surface for a metal–insulator–semiconductor high electron mobility transistor (MIS HEMT). The FG-MIS HEMT achieves better DC characteristics than a traditional MIS HEMT, including larger saturation drain current density (34.3%), higher peak trans-conductance (14.4%), lower ON-resistance (21.6%), and lower off-state leakage. Moreover, current collapse measurement reveals that not only can FG suppress the drain saturation current reduction of MIS HEMT from 41.8% to 8.1% at off-state drain bias of 50 V, but also it prevents dynamic ON-resistance increasing with off-state stress. The coverage of FG on GaN surface can prevent GaN being oxidized and N diffusion from GaN during gate dielectric deposition, thus suppressing the formation of Ga-O bonds and Ga dangling bonds, leading to an excellent interface condition for Al2O3/GaN with reduced fixed interface charges. Therefore, significant passivation effect is achieved.

(Invited) Electrothermal Performance Optimization of III-Nitride HEMTs Capped with Nanocrystalline Diamond

AlGaN/GaN high electron mobility transistors (HEMT) capped with nanocrystalline diamond (NCD) have been demonstrated in the past to outperform electrically and thermally their SiN-passivated counterparts [1, 2]. However, a major process limitation for the integration of a diamond heat spreader has been the O2-plasma damage in the gate opening associated with etching the diamond cap. To reduce plasma damage, Anderson et al. have demonstrated a two-step diamond etch process, where the plasma power is reduced towards the end of the etch to minimize damage to the AlGaN surface [3]. While this process has enabled improved electrical performance of NCD-capped HEMTs, optimal passive heat spreading requires NCD films thicker than 0.5 µm which challenges the two-step etch approach [4]. Further complications such as on-wafer variations in NCD thickness have motivated the search for a more robust gate process. Recently, we have proposed the use of a sacrificial gate (SG) prior to diamond growth [5, 6]. The SG stack consisted of a 10 nm thick ALD-grown Al2O3 layer followed by a 100 nm thick PECVD-grown SiNx layer. The SiNx layer served as an etch stop for the NCD layer, and the Al2O3 served as an etch stop for the SiNx layer. The Al2O3/SiNx stack was patterned with the dimensions of the gate and a blanket 500 nm thick CVD NCD film was conformally-grown over the feature. The gate feature was then realigned and a high power O2-plasma was used to clear the NCD film in the gate region. This resulted in a much more reliable gate opening since the window for NCD over-etch was much larger. The sacrificial SiNx finger was subsequently etched away using a SF6-ICP process. The Al2O3 layer was removed in dilute HF solution with no measureable degradation to the rest of the device. Finally, the Ni/Au gate metal stack was lifted off. On HEMTs with a SG, the addition of a NCD cap did not cause any significant degradation in mobility, carrier density, or sheet resistance. By contrast, when a SG process was not used to protect the AlGaN surface, the NCD-capped HEMT experienced a decrease in mobility and an increase in sheet resistance. For the SG NCD-capped HEMT, the off-state current increased by less than an order of magnitude and threshold voltage shifted by about 1 V. However, on-state drain current levels remained comparable and degradation in dynamic on resistance (RON,DYN) upon an off-state drain bias stress was improved, indicating potential improvement in AlGaN surface passivation by the NCD film [2, 3]. Such improvement is also corroborated by the improvement in breakdown voltage in NCD-capped HEMTs with a conventional gate opening design. This presentation will review progress in simulation, process integration, channel temperature mapping, and electrical characterization of diamond-capped devices. We will also review several novel NCD concepts, such as in-plane control of NCD thermal conductivity, as well as a diamond-gated AlGaN/GaN HEMT [7, 8]. [1] M.J. Tadjer, et al., IEEE Electron Dev. Lett., vol. 33, no. 1, pp. 23-25, 2012. [2] D.J. Meyer, et al., IEEE Electr. Dev. Lett., vol. 35, no. 10, pp. 1013, 2014. [3] T.J. Anderson et al., 70th Dev. Research Conf. Proc., pp. 155-156, 2012. [4] A. Wang, M.J. Tadjer, and F. Calle, Semicond. Sci. Technol., vol. 28, pp. 055010 (2013). [5] T.J. Anderson et al., CS Mantech Conf. Digest, pp. 205-208, 2013. [6] M.J. Tadjer, et al., Phys. Status Solidi A, 2015, in press. [7] T.J. Anderson, et al., IEEE Electr. Dev. Lett., vol. 34, no. 11, pp. 1382, 2013. [8] J. Anaya et al., Acta Materialia 103 (2016) 141-152.

Studies on High-Voltage GaN-on-Si MIS-HEMTs Using LPCVD Si3N4as Gate Dielectric and Passivation Layer

This paper investigates the performance of AlGaN/gallium nitride (GaN) MIS high electron mobility transistors (MIS-HEMTs). The gate dielectric layer and the surface passivation layer are formed by the low-pressure chemical vapor deposition (LPCVD) Si3N4. The LPCVD-Si3N4 MIS-HEMTs exhibit a high breakdown voltage (BV) of 1162 V at $I_{\mathrm{ DS}}= 1~\mu \text{A}$ /mm, a low OFF-state leakage of $7.7 \times 10^{-12}$ A/mm, and an excellent ON/OFF-current ratio of $\sim 10^{11}$ . Compared with the static ON-resistance of 2.88 $\text{m}\Omega \cdot \textrm {cm}^{2}$ , the dynamic ON-resistance after high OFF-state drain bias stress at 600 V only increases to 4.89 $\text{m}\Omega \cdot \textrm {cm}^{2}$ . The power device figure of ${\mathrm{ merit}} = \textrm {BV}^{{\vphantom {R^{l}}{2}}}/R_{{{\mathrm{\scriptscriptstyle ON}.{\mathrm{ sp}}}}}$ is calculated to be 469 $\textrm {MW}\cdot \textrm {cm}^{-2}$ . The LPCVD-Si3N4/GaN interface state density is in the range of (1.4–5.3) $\times 10^{{\vphantom {R^{l}}{13}}}$ eV $^{-1}$ cm $^{-2}$ extracted by the conventional conductance method. Finally, the gate insulator degradation of GaN-based MIS-HEMTs is analyzed by time-dependent dielectric breakdown test. The lifetime is extrapolated to 0.01% of failures after ten years at 300 K by fitting the data with a power law to a gate voltage of 10.1 V.

Optical pumping of deep traps in AlGaN/GaN-on-Si HEMTs using an on-chip Schottky-on-heterojunction light-emitting diode

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoH-LED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The de-trapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs.

Enhancement-mode metal–insulator–semiconductor GaN/AlInN/GaN heterostructure field-effect transistors on Si with a threshold voltage of +3.0 V and blocking voltage above 1000 V

Enhancement-mode AlInN/GaN metal–insulator–semiconductor heterostructure field-effect transistors on silicon are reported. A fluorine-based plasma treatment and gate dielectric are employed, and the devices exhibit a threshold voltage of +3 V. A drain current density of 295 mA/mm for a gate bias of +10 V is measured. An excellent off-state blocking voltage capability of 630 V for a leakage current of 1 µA/mm, and over 1000 V for 10 µA/mm are achieved on a 20-µm-gate–drain separation device at gate bias of 0 V. The dynamic on-resistance is ∼2.2 times the DC on-resistance when pulsing from an off-state drain bias of 500 V.

Increased static R ON in GaN‐on‐silicon power transistors under high‐side operation with floating substrate conditions

An increase in static on-state resistance ( R ON ) is observed in heterojunction field-effect transistors (HFETs) fabricated as GaN-on-silicon devices with floating substrates, when the device is operated at a higher positive bias with respect to the ground, compared to nominal grounded source measurement conditions. This is unlike the widely discussed and reported phenomenon of dynamic R ON increase during current collapse, where an increase in R ON is observed only after a high off-state drain bias is applied to the device. These findings are crucial from the point of view of in power electronic circuit applications either as discrete devices or in monolithic integrated circuits. The impact manifests itself as an increased threshold voltage in the HFET and affects its output characteristics, with an impact equivalent to and observed during Si substrate negative back-biasing.

Study of the leakage current suppression for hybrid-Schottky/ohmic drain AlGaN/GaN HEMT

The leakage current suppression mechanism in AlGaN/GaN High Electron Mobility Transistors (HEMTs) is investigated. It is known that leakage current can cause severe reliability problems for HEMT devices and conventional AlGaN/GaN HEMT devices suffer from detrimental off-state drain leakage current issues, especially under high off-state drain bias. Therefore, a leakage current suppression technique featuring hybrid-Schottky/ohmic-drain contact is discussed. Through the 2-zones leakage current suppression mechanism by the hybrid-Schottky/drain metal including the shielding effect of the rough ohmic-drain metal morphology and the drain side electric field modulation, AlGaN/GaN HEMT featuring this novel technique can significantly enhance the leakage current suppression capability and improve the breakdown voltage. An analytical method using loop-voltage-scanning is proposed to illustrate the optimization procedure of the hybrid-Schottky/ohmic drain metallization on leakage current suppression. Through the comparison of the loop leakage current hysteresis of conventional ohmic drain HEMT and hybrid-Schottky/ohmic drain, the leakage current suppression mechanism is verified through the leakage current considering surface acceptor-like trap charging/discharging model. Device featuring the hybrid-Schottky/ohmic drain technique shows an improvement in breakdown voltage from 450V (with no Schottky drain metal) to 855V with a total drift region length of 9μm, indicating enhanced off-state reliability characteristics for the AlGaN/GaN HEMT devices.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Normally-off GaN Transistors for Power Applications

Normally-off high voltage GaN-HFETs for switching applications are presented. Normally-off operation with threshold voltages of 1 V and more and with 5 V gate swing has been obtained by using p-type GaN as gate. Different GaN-based buffer types using doping and backside potential barriers have been used to obtain blocking strengths up to 1000 V. The increase of the dynamic on-state resistance is analyzed for the different buffer types. The best trade-off between low dispersion and high blocking strength was obtained for a modified carbon-doped GaN-buffer that showed a 2.6x increase of the dynamic on-state resistance for 500 V switching as compared to switching from 20 V off-state drain bias. Device operation up to 200 °C ambient temperature without any threshold voltage shift is demonstrated.

High-Voltage (600-V) Low-Leakage Low-Current-Collapse AlGaN/GaN HEMTs with AlN/SiNx Passivation

An effective passivation technique that yields low off-state leakage and low current collapse simultaneously in high-voltage (600-V) AlGaN/GaN high-electron-mobility transistors (HEMTs) is reported in this letter. The passivation structure consists of an AlN/SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> stack with 4-nm AlN deposited by plasma-enhanced atomic layer deposition and 50-nm SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> deposited by PECVD. The AlN/ SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> -passivated HEMTs with a gate-drain distance of 15 μm exhibit a high maximum drain current of 900 mA/mm, a low off-state current of 0.7 μA/mm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 600 V, and a steep subthreshold slope of 63 mV/dec. Compared with the static on-resistance of 1.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the dynamic on-resistance after high off-state drain bias stress at 650 V only increases to 2.1 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A high breakdown voltage of 632 V is achieved at a drain leakage current of 1 μA/mm .