Numerical Device Simulation Research Articles

A data-driven compact drain current model for InGaAs FinFET using TCAD assisted machine learning approach

Abstract This article presents a novel machine learning-based framework for modeling the drain current of InGaAs FinFETs. An artificial neural network, trained on a comprehensive dataset generated by 3D numerical device simulations, forms the core of this model. The simulations covered a wide range of device geometries and bias conditions, resulting in diverse current-voltage characteristics. Using TensorFlow in a Python environment, we built and trained a neural network to accurately predict drain current. The model’s performance was evaluated on independent test datasets, demonstrating its effectiveness on unseen data. The model accurately captures the effects of varying gate length, drain voltage, and gate voltage. Multiple error metrics, including mean squared error, mean absolute error, root mean squared error, and correlation coefficient, were used to assess its performance. At shorter gate lengths, the calculated relative error in drain current was 2.18% and 1.17% at VDS=50mV and 1V, respectively.
After training, the network parameters were extracted to create a Verilog-A model. This model was integrated into the SPICE simulator for circuit simulations. A resistive load inverter circuit was designed to demonstrate the model’s capabilities, and voltage
transfer characteristics and transient analysis were performed within SPICE. These results validate the effectiveness of the developed machine learning-based InGaAs FinFET model.

Insights into the Heat‐Assisted Intensive Light‐Soaking Effect on Silicon Heterojunction Solar Cells

Heat‐assisted intensive light soaking has been proposed as an effective posttreatment to further enhance the performance of silicon heterojunction (SHJ) solar cells. In the current study, it is aimed to distinguish the effects of heat and illumination on different (doped and undoped) layers of the SHJ contact stack. It is discovered that both elevated temperature and illumination are necessary to significantly reduce interface recombination when working effectively together. The synergistic effect on passivation displays a thermal activation energy of approximately 0.5 eV. This is likely due to the photogenerated electron/hole pairs in the c–Si wafer, where nearly all of the incident light is absorbed. By distinguishing between the effects of light and heat effects on the conductivity of p‐ and n‐type doped hydrogenated amorphous silicon (a–Si:H) layers, it is demonstrated that only heat is accountable for the observed rise in conductivity. According to numerical device simulations, the significant contribution to the open‐circuit voltage enhancement arises from the reduced density of defect states at the c–Si/intrinsic a–Si:H interface. In addition, the evolution of the fill factor is highly dependent on changes in interface defect density and the band tail state density of p‐type a–Si:H.

Nanoscale Trench Gate Engineered JAM Gate-All-Around (TGE-JAM-GAA) Label-Free BioFET for Charged/Neutral Biomolecules Detection

In this manuscript, a Trench Gate Engineered Junctionless Accumulation Mode Gate-All-Around (TGE-JAM-GAA) BioFET structure has been proposed and critically analyzed for the label-free identification of biomolecules using extensive numerical device simulations. This device is superior in terms of a variety of performance metrics, including higher sensitivity, a larger shift in threshold voltage, drain current, transconductance, and the ION/IOFF current ratio. These improvements are due to both the triple metal gate engineering and the trench gate. A comparative analysis of TGE-JAM-GAA BioFET has been performed with a triple metal normal gate JAM Gate-All-Around FET (TMNG-JAM-GAAFET) and a conventional single metal normal gate JAM Gate-All-Around FET (SMNG-JAM-GAAFET) biosensor. For instance, in the case of APTES biomolecules, the drift in threshold voltage obtained is 236.24 mV, which is 58.75% and 159.18% higher than that of the TMNG-JAM-GAAFET and SMNG-JAM-GAAFET, respectively, demonstrating that the TGE-JAM-GAA BioFET is more suitable for applications in biosensing.

6‐1: Pragmatic low‐temperature polycrystalline thin‐film transistor technologies for high‐brightness and high‐temperature environments in AMOLED displays

This paper presents experimental and theoretical analysis of electrical characteristics for recent process‐based low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) in AMOED displays, focusing on high‐temperature and high‐luminance device characteristics. All off‐state current (Ioff) components in such conditions, which include gate‐induced drain leakage (GIDL), thermal generation, photo generation currents, are in detail analyzed. Exploring the effects of process technologies and device design in small‐size TFTs, in conjunction of reduced defect density‐of‐state (DOS) in the polycrystalline and its interface of gate oxide, we investigate optimal device and process design for reliable polycrystalline thin‐film transistor technologies in high‐brightness and high‐temperature situations. Numerical device simulations, supplemented by physics‐based analysis, confirm experimental results for our optimized device/process and gain diligent process/ design co‐optimization insights.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Catalytic Metal‐Gated Nano‐Sheet Field Effect Transistor and Nano‐Sheet Tunnel Field Effect Transistor Based Hydrogen Gas Sensor‐ A Design Perspective

AbstractIn this work, for the first time, the catalytic metal gate (CMG) based nanosheet Field Effect Transistor (NSFET) and nanosheet Tunnel Field Effect Transistor (NSTFET) are proposed for nano‐scale device dimensions, and the different design aspects of catalytic metal gate (CMG)‐based transduction for Hydrogen (H2) sensing are extensively investigated using numerical device simulation. The influence of applied biasing conditions and structural parameter specifications on the sensing performance of CMG‐NSFET and CMG‐NSTFET are methodically analyzed from device electrostatics and carrier transport mechanisms. Furthermore, the relative maximum sensitivity variations with H2‐partial pressure, ambient temperature, and the presence of ambient Oxygen are comprehensively studied. The study reveals that compared to CMG‐NSFET, the CMG‐NSTFET demonstrates a high immunity against bias and doping variations, with a notably higher (> 50%) sensitivity within low H2 partial pressures (10−15 – 10−10 Torr). Next, the sensing performance of CMG‐NSTFET is systematically optimized through a band‐gap and gate‐stack engineering approach, leading to a 180% to 650% sensitivity improvement from lower (10−15 Torr) to higher (10−5 Torr) range of H2 partial pressure. Finally, the performance of optimized CMG‐NSFET and CMG‐NSTFET are extensively benchmarked against other reported nanostructured CMG‐FET and TFET‐based H2 gas sensors, exhibiting a notably higher sensitivity in the proposed sensors.

Integration of Machine Learning with Statistical Variation Analysis for Ferroelectric Transistor (FE-MOSFETs)

This paper investigates a comparative analysis of technology computer-aided design (TCAD) versus machine learning (ML) technique for ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET), which shows the low power energy storage device and ML algorithms reduce the time or overall process. The simulations carried out through TCAD require approximately 44–46 days, encompassing variations in input parameters like gate work function ([Formula: see text]), doping concentration ([Formula: see text]), channel doping ([Formula: see text]), gate-to-source voltage ([Formula: see text]), and drain-to-source voltage ([Formula: see text]). In order to lower the computing cost of numerical TCAD device simulations, a new ML-assisted technique is provided for studying the FE-MOSFET. To reduce the runtime of physics-based TCAD by about 10–12[Formula: see text]h for each iteration, a ML-based prediction alternative is created. The proposed combination of TCAD device simulation and ML algorithms is the future of the next generation of electronics.

Physics-based analytical model for trap assisted biosensing in dual cavity negative capacitance junctionless accumulation mode FET

The design of a ferroelectric-based biosensor for detecting various biomolecules like proteins and DNA has captivated the interest of researchers in early disease diagnostics and treatment monitoring. Doomed by this interest, an analytical model for trap-assisted biosensing in Dual Cavity Negative Capacitance Junctionless Accumulation Mode FET is proposed for detecting various biomolecules. The biomolecules are treated as traps that tunnel through the biosensor's ferroelectric layer. The analytical model is validated through extensive numerical device simulations. The device incorporates the detection of charged and uncharged biomolecules in terms of dielectric constants and biomolecule concentration. The nano-cavities are created inside the gate dielectric stack to collect biomolecules like proteins and DNA. As the biomolecules are infused as traps in cavity areas, electrical properties of the biosensor, like input characteristics, transconductance, threshold voltage, on-state current, and subthreshold swing change. The sensitivity obtained for the proposed biosensor is compared with the existing biosensor and found that it is best suited for susceptible biosensing applications.

A Surface Potential Model for Metal-Oxide-Semiconductor Transistors Operating near the Threshold Voltage

Device physics and accurate transistor modeling are necessary to reduce the operating voltage near the threshold for power-constrained circuits. Conventional device modeling for metal-oxide-semiconductor (MOS) transistors focuses on operations in either strong or weak inversion regimes, and the electrostatics at gate biases near the threshold voltage is rarely studied. This research proposed an analytical model to describe the distribution of the surface potential along the channel for near-threshold operation. Numerical device simulations were also performed to investigate the electrostatics near the threshold voltage. The numerical simulation with constant carrier mobility showed an overshoot in the transconductance due to decay of the lateral electric field with gate bias. The decay of the lateral electric field was predicted by the proposed analytical surface potential model which considered widening the channel length with flooding of the inversion carriers in the channel and gate overlap regions. The channel length widening effect saturated as the gate bias further increased. Therefore, evident transconductance overshoot was observed near the threshold voltage in short-channel devices.

Enhancing the Selectivity and Transparency of the Electron Contact in Silicon Heterojunction Solar Cells by Phosphorus Catalytic Doping

AbstractAn intrinsic hydrogenated amorphous silicon (a‐Si:H(i)) film and a doped silicon film are usually combined in the heterojunction contacts of silicon heterojunction (SHJ) solar cells. In this work, a post‐doping process called catalytic doping (Cat‐doping) on a‐Si:H(i) is performed on the electron selective side of SHJ solar cells, which enables a device architecture that eliminates the additional deposition of the doped silicon layer. Thus, a single phosphorus Cat‐doping layer combines the functions of two other layers by enabling excellent interface passivation and high carrier selectivity. The overall thinner layer on the window side results in higher spectral response at short wavelengths, leading to an improved short‐circuit current density of 40.31 mA cm−2 and an efficiency of 23.65% (certified). The cell efficiency is currently limited by sputter damage from the subsequent transparent conductive oxide fabrication and low carrier activation in the a‐Si:H(i) with Cat‐doping. Numerical device simulations show that the a‐Si:H(i) with Cat‐doping can provide sufficient field effect passivation even at lower active carrier concentrations compared to the as‐deposited doped layer, due to the lower defect density.

Effects of material doping on the performance of thermoelectric generator with/without equal segments

Thermoelectricity is a clean energy source that has garnered attention worldwide. Improving the performance of thermoelectric devices to convert waste heat into electricity efficiently is currently a priority for many researchers. One way to do this is by improving the thermoelectric performance of the materials used in thermoelectric generators (TEGs). In recent years, doping different materials into thermoelectric materials to enhance TEG's performance has attracted attention. This study analyzes the improvement of TEGs by performing 3D numerical simulations of thermoelectric devices using a series of SnTe with different doping levels. The results show that the undoped SnTe-AgSbSe2 composite has the highest output power compared with the doped case. In terms of conversion efficiency, the composite AgSbSe2 doped with 3% SnTe achieves the highest conversion efficiency. Furthermore, the performance comparison with conventional TEG shows that the equal segmented thermoelectric generator (STEG) has higher output power and conversion efficiency at all doping ratios. In addition, the SnTe-AgSbSe2 composite with 3% doping concentration has the best thermoelectric performance with an output power of 64.49 mW and an efficiency of 14.17% at a temperature difference of 500 K (a hot side temperature of 800 K and a cold side temperature of 300 K). Accordingly, it is summarized that the combination of doped SnTe thermoelectric material and equal-STEG design can efficiently enhance the thermoelectric module's (TEM) performance.

Design and analysis of Z shaped InGa0.5As0.5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application

—In this paper, a high-k stacked gate Z shaped hetero-juncture TFET (Z-HTFET) is introduced as transducer sensor for the application of hydrogen gas detection. The positioning of stacked gate over the entire source region resulting Z shaped TFET exhibits vertical line tunneling mechanism between the source and the channel yielding higher ON state current (Id) as compared to conventional double gate (DG) TFET. Further, the combination of low band gap source of In0.5Ga0.5As and hetero-gate dielectric engineering helps to facilitate improved device current, steeper subthreshold slope and lower leakage current (Ileak) conduction. Here, palladium (Pd) and the high-k gate stack (HfO2/SiO2) is used as the sensing platform. The induced shift in work function of Pd gate electrode due to the dissociation and diffusion of hydrogen gas molecules into the catalytic gate metal is considered as the detection metric for calculating the sensitivity of the proposed TFET based gas sensor. The behavior of the hydrogen gas sensor is studied using numerical device simulator in terms of surface potential, electric field, transfer characteristics, transconductance, Id/Ileak ratio with variation in work-function and finally Id/Ileak sensitivity is measured. The sensor behavior for a wide range of temperature is also examined to explore the temperature stability of the device. The comparative performance analysis of Z-HTFET with sensitivity of 95.26% establishes the superiority of the device for hydrogen gas sensing as compared to some of the recently reported FET based sensors.

Analysis of multilayer OLED for improvement in drive current and luminescent power

This research paper discusses the performance enhancement techniques of multi-layered OLED structures. OLED’s electrical behaviour is evaluated using an analytical model using benchmarked industry-standard Atlas 2-D numerical device simulator. It highlights the extraction of emission and charge transport phenomena and charges injection role. Multilayer OLED device has been investigated by extracting the key performance parameters, including the current density and luminescent power as a function of anode voltage. There is an improvement of 15% in the current density. Furthermore, this work has proceeded with internal analysis and using a mathematical model, where the electric field, total current density, electron and hole concentration, and internal device parameters have been extracted to understand the performance of OLED devices better. Additionally, the internal physics and behaviour of the device have been studied in terms of Langevin recombination. Internal analysis is performed by making cutlines in a vertical fashion so that device physics and the process occurring in the internal part can be clearly understood. The OLED device behaviour analysis is performed using the industry standard state of art device simulation tool.

A Novel Approach for Designing a Sub-Bandgap in CuGa(S,Te)2 Thin Films Assisted with Numerical Simulation of Solar Cell Devices for Photovoltaic Application.

As a well-explored chalcopyrite material, copper gallium sulfide CGS has been considered a potential material for solar cell absorber layers. However, its photovoltaic attributes still require to be improved. In this research, a novel chalcopyrite material, copper gallium sulfide telluride CGST, has been deposited and verified as a thin film absorber layer to fabricate high-efficiency solar cells by experimental testing and numerical simulations. The results display the intermediate band formation in CGST with incorporation of Fe ions. Electrical studies showed enhancement in mobility from 1.181 to 1.473 cm2 V-1 s-1 and conductivity from 2.182 to 5.952 S cm-1 for pure and 0.08 Fe-substituted thin films. The I-V curves display the photoresponse and ohmic nature of the deposited thin films, and the maximum photoresponsivity (0.109 A W-1) was observed for 0.08 Fe-substituted films. Theoretical simulation of the prepared solar cells was carried out using SCAPS-1D software, and the obtained efficiency displayed an increasing trend from 6.14 to 11.07% as the Fe concentration increased from 0.0 to 0.08. This variation in efficiency is attributed to the decrease in bandgap (2.51-1.94 eV) and the formation of an intermediate band in CGST with Fe substitution, which is evidenced in UV-vis spectroscopy. The above revealed results open the way to 0.08 Fe-substituted CGST as a promising candidate as a thin film absorber layer in solar photovoltaic technology.

40‐3: Distinguished Paper: Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

This paper presents recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. Experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. Process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction of improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs, as well as gain more physical insight in the bottom‐gate LTPS device configuration, to enable reliable low‐power high‐performance AMOLED display applications.

Design technique co-optimization approach to GAA FETs for inverter design at advanced technology node

Gate-all-around Nanosheet field-effect transistor (GAA-NSFET) is a potential replacement for the state-of-art FinFET devices at advanced technology nodes. In this article, the impact of process-induced variability such as gate work function variation (WFV) on NSFETs using 3D TCAD numerical device simulation is studied. The WFV of NSFETs and NWFETs using multiple stack channels are also analyzed. The fluctuation in the threshold voltage (σVTH) and on-current (σION) of NSFETs is mainly affected by the WFV of the metal gate. It is investigated that single and 3-stacked NSFET shows superior immunity to WFV compared to NWFET. Furthermore, a layout-based NSFET inverter design using the DTCO technique is followed and the advantages of the stacked NSFET in terms of delay, power dissipation and switching energy are also reported.

Investigation of transient response on reconfigurable ringFET exposed to heavy-ion radiation strikes using 3D numerical device simulations

Investigation of transient response on reconfigurable ringFET exposed to heavy-ion radiation strikes using 3D numerical device simulations

Reliable low‐power high‐performance low‐temperature polycrystalline thin‐film transistor technologies in bottom gate‐controlled device architectures for AMOLED displays

AbstractThis paper presents a recent process for bottom gate‐controlled low‐temperature polysilicon (LTPS) TFT technologies for reliable low‐power high‐performance AMOLED displays. The experimental and physics‐based analysis leads to the pragmatic device design concept for LTPS TFT performance enhancement. The process integration of bottom (second) gate and top (first) gate metals, controlled by optimal two gates‐based device structures, is explored in conjunction with improved poly crystallization and poly‐Si/gate‐oxide interface by reducing defect density‐of‐state (DOS), especially in the grain boundaries of the channel region. We obtain optimal device performance, such as optimal sub‐threshold slope, high driver current (Ion), and low leakage current (Ioff), in addition to enhanced device reliability characteristics. Numerical device simulations, supplemented by physics‐based analysis, are performed to corroborate experimental results in fabricated TFTs and gain more physical insight into the bottom‐gate LTPS device configuration to enable reliable low‐power high‐performance AMOLED display applications.

Simulation of Continuous Phase Flow in Small‐Scale Vortex Devices: Model Applicability Assessment

AbstractTo investigate the applicability of flow models used for numerical simulation of vortex devices, reorganization group k‐ε, Reynolds stress model, delayed detached eddy simulation (DDES), and large eddy simulation were evaluated for small‐scale vortex reactors/separators. Their comprehensive performances were compared in terms of the assessment indicators including root mean squares error, coefficient of determination R2, and convergence time. It was found that considering the balance of techno‐economics, DDES is the better option with relatively high prediction accuracy (RMSE = 0.5577 and R2 = 0.9591) and low computational cost (∼500 s) under a specified computational platform. The results can provide a positive reference for the selection and improvement of the flow models used for vortex devices.

Switching performance assessment of gate-all-around InAs–Si vertical TFET with triple metal gate, a simulation study

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a triple metal gate (VTG-TFET). We obtained improved switching characteristics for the proposed design because of the improved electrostatic control on the channel and the narrow bandgap source. It shows an Ion of 392 μA/μm, an Ioff of 8.8 × 10−17 A/μm, an Ion/Ioff ratio of about 4.4 × 1012, and a minimum subthreshold slope of 9.3 mV/dec at Vd = 1 V. We also analyze the influence of the gate oxide and metal work functions on the transistor characteristics. A numerical device simulator, calibrated to the experimental data of a vertical InAs–Si gate all around TFET, is used to accurately predict different features of the device. Our simulations demonstrate that the proposed vertical TFET, as a fast-switching and very low power device, is a promising transistor for digital applications.