Number Of Test Configurations Research Articles

An Integrated Framework for Application Independent Testing of FPGA Interconnect

This paper presents a FPGA interconnect test configuration generation strategy for application-independent testing using Satisfiability (SAT). The technique generates all possible path configurations for the interconnect to obtain full coverage of all interconnect resources. The integrated testing approach is proposed which generates test vectors and path configurations in a single phase, thus obtaining a significant reduction in the number of test configurations needed to test the circuit. To generate test configurations, constraints have been designed using SAT. The proposed technique targets open and short faults in the interconnect resources. Test configurations have been generated for different FPGA architectures. The objective of the proposed approach is to minimize the number of configurations without reducing the fault coverage.

Aero-elastic testing of multi-spanned transmission line subjected to downbursts

This paper reports the first aero-elastic test conducted under a scaled downburst wind field at the WindEEE dome facility at the University of Western Ontario, Canada. The main purpose of the test is to assess the dynamic response of a multi-span transmission line. The study starts by providing a characterization of the downburst wind field produced in WindEEE including a comparison with results of previously conducted numerical simulations. A number of test configurations, involving different locations of the downburst relative to the line, is considered. A decomposition approach is developed to separate between the resonant and the background components of the response. The results are presented in the form of a dynamic magnification factor that relates the peak response including the dynamic effect to the maximum quasi-static response. The test results show that the resonance contribution ranges between 5% and 10% of the peak response for the tower. They also show that the dynamic response of the conductors can reach up to 30% and 12% of the peak response at low and high downburst speeds, respectively.

Experimental and numerical investigations of cooling drag

As the target figures for CO2 emissions are reduced every year, vehicle manufacturers seek to exploit all possible gains in the different vehicle attributes. Aerodynamic drag is an important factor that affects the vehicle’s fuel consumption, and its importance rises with the shift from the New European Driving Cycle to the Worldwide harmonized Light vehicles Test Cycle which has a higher average speed. In order to reduce vehicle drag, car manufacturers employ the use of grill/spoiler shutters which reduces the amount of air going through the vehicle’s cooling system, also known as cooling flow, thus reducing both its cooling capability and the resultant cooling drag. This paper investigates the influence of different grill blockages on the cooling flow through the radiator of a Volvo S60. By modifying the engine bay and radiator, load cells are used to measure the force acting on the radiator core while the velocity distribution across the radiator core is measured using pressure probes. These values are analyzed and compared to different vehicle configurations and grill inlet designs. A number of test configurations are reproduced in Computational Fluid Dynamics simulations and compared to the test results. For some grill configurations, the simulations provide a good prediction of mass flow and velocity distribution; however a clear discrepancy is present as the grill blockages increase. On the other hand, the force acting on the radiator core was well predicted for all configurations. This paper discusses the different parameters affecting cooling flow predictions such as wind tunnel blockage and measurement grid discretization by comparing radiator forces and mass flows. In addition, the changes on overall vehicle forces are discussed with the radiator force put in context with cooling drag.

A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect

FPGA test cost can be reduced effectively by minimizing the number of test configurations. To realize it, a self-configurable structure was proposed before to test the cross-point-based switch box in FPGA. In this paper, a technique of partially self-configurable multiplexers is presented to reduce the test cost of completely multiplexer-based FPGA interconnect cost-efficiently. The additional self-configured structure, called test point here, is only added to the most efficient configuration ports, which is selected through analyzing test configurations, so the test cost can reduce with the minimal area overhead. It is shown that for testing all interconnect stuck-at faults in FPGAs like Virtex-II and Spartan-3 the test configurations can be reduced to 8 with merely about 1.2% area penalty.

Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics

In this paper, a built-in self-test (BIST) procedure is proposed for testing and fault tolerance of molecular electronics-based nanofabrics. The nanofabrics are assumed to include up to 1012 devices/cm2; this requires new test strategies that can efficiently test and diagnose the nanofabrics in a reasonable time. Our BIST procedure utilizes nanofabric components as small test groups containing test pattern generator and response analyzer. Small test groups (fine-grained test) result in higher diagnosability and recovery. The proposed technique applies the test in parallel with a low number of test configurations resulting in a manageable test time. Due to high defect density of nanofabrics, an efficient diagnosis procedure is done after BIST procedure to achieve high recovery. This is called recovery-increase procedure, and this increases the available number of fault-free components detected in a nanochip. Finally, a defect database called defect map is created to be used by compilers during the configuration of the nanofabrics to avoid defective components. This results in a reliable system constructed from unreliable components. Our simulation results demonstrate the effectiveness of the proposed BIST and recovery-increase procedures

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.

SRAM-Based FPGAs: Testing the Embedded RAM Modules

This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called ‘pseudo shift register’ for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called ‘shifted MATS++’ is described.

Multiaxial fatigue of steel—testing out of phase and in blocks: validity and applicability of some criteria

The criteria used to calculate the dimensions of specimens under multiaxial fatigue are compared with some particularly unusual or discriminating test results. Tests carried out with combined loadings and in blocks of different loadings, and some tests on data in published work enable us to define the area of application and the validity of criteria. The most widely used approach, with two stresses applied to one specific facet, is shown to be inaccurate in a number of test configurations. An energy-based approach would seem to be more appropriate.

Further development of the helical extension spring: Huhnen, J. Wire Nov. 1990 40, (6), 622–624

The criteria used to calculate the dimensions of specimens under multiaxial fatigue are compared with some particularly unusual or discriminating test results.Tests carried out with combined loadings and in blocks of different loadings, and some tests on data in published work enable us to define the area of application and the validity of criteria.The most widely used approach, with two stresses applied to one specific facet, is shown to be inaccurate in a number of test configurations. An energy-based approach would seem to be more appropriate.