A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect

Abstract

FPGA test cost can be reduced effectively by minimizing the number of test configurations. To realize it, a self-configurable structure was proposed before to test the cross-point-based switch box in FPGA. In this paper, a technique of partially self-configurable multiplexers is presented to reduce the test cost of completely multiplexer-based FPGA interconnect cost-efficiently. The additional self-configured structure, called test point here, is only added to the most efficient configuration ports, which is selected through analyzing test configurations, so the test cost can reduce with the minimal area overhead. It is shown that for testing all interconnect stuck-at faults in FPGAs like Virtex-II and Spartan-3 the test configurations can be reduced to 8 with merely about 1.2% area penalty.