Number Of Processing Elements Research Articles

A parallel strategy and performance analysis of the EM-like reconstruction method for diffuse optical tomography

The EM-like reconstruction method for steady state diffuse optical tomography is a propagation back-propagation method and its sequential implementation requires excessively longer computation time. Hence we apply a parallel strategy to the reconstruction method. We divide the groups of boundary measurements into several nonoverlapping subsets and each subset of boundary measurements are handled by selected processing element. We take two-dimensional numerical experiments on a single Symmetric Multi-Processing system to test the performance of the parallel strategy. The computation time of the parallel implementation indicates that high performance of computation can be obtained. Besides, the more groups of boundary measurements are used for the reconstruction, the higher speed-up and parallel efficiency can be achieved. Due to the usage of memory, the curve of speed-up with respect to different numbers of processing elements appears a wave pattern while the curve of efficiency with respect to different numbers of processing elements decreases rapidly. Thus, for three-dimensional reconstruction problem, we can execute the parallel reconstruction scheme on a cluster which aligns multiple workstations by a network.

The fast evolving landscape of on-chip communication

As multi-core systems transition to the many-core realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while--at the same time--technological and application constraints increase the pressure for increased performance and efficiency with limited resources. Although NoC research has evolved significantly the last decade, essential questions remain un-answered and call for fresh research ideas and innovative solutions. In this paper, we summarize a selected set of NoC-related research challenges, with the hope to guide future development and trigger high-impact research progress.

Perfectly Load-Balanced, Stable, Synchronization-Free Parallel Merge

We present a simple, work-optimal and synchronization-free solution to the problem of stably merging in parallel two given, ordered arrays of m and n elements into an ordered array of m+n elements. The main contribution is a new, simple, fast and direct algorithm that determines, for any prefix of the stably merged output array, the exact prefixes of each of the two input arrays needed to produce this output prefix. More precisely, for any given index in the resulting, but not yet constructed output array, representing the desired output prefix, the algorithm computes the indices (called co-ranks) in each of the two input arrays representing the required input prefixes without having to merge the input arrays. The co-ranking algorithm takes [Formula: see text] time steps, and uses O(1) space. Co-ranking is used in parallel to partition the input arrays into a collection of as many pairs as desired, each pair with exactly the same number of elements. Any stable, sequential merge algorithm can be used to merge pairs independently. The result is a perfectly load-balanced, stable, parallel merge algorithm. Co-ranking and sequential merging of pairs can be done without synchronization. Compared to other, linear speed-up approaches to the parallel merge problem, the algorithm is considerably simpler and can be up to a factor of two faster. Compared to previous algorithms for solving the co-ranking problem, the new algorithm works for arbitrary output array indices and maintains stability in the presence of repeated elements at no extra space or time cost. When the number of processing elements p does not exceed (m + n)/ log min(m, n), the parallel merge algorithm has perfect, linear speedup p. Furthermore, it is easy to implement on both shared and distributed memory systems.

Differentiated Communication Services for NoC-Based MPSoCs

The adoption of Networks-on-Chip (NoCs) as the communication infrastructure for complex integrated systems is a fact, and has been promoted by the growing number of processing elements integrated in current MPSoCs. These are designed to execute several applications in parallel, with different communication requirements and distinct levels of required quality of service. To meet these restrictions, most designs customize the MPSoC at design time, using specific NoC communication services as adaptive routing algorithms, priorities, and connections. However, MPSoCs are increasingly used in embedded systems, where new applications may be added at runtime, characterizing dynamic workload scenarios. Such scenarios require adaptability at runtime, with applications having the possibility to select the most appropriate communication service according to their respective requirements. The goal of the present work is to link the hardware level of NoCs to the MPSoC application level, proposing the development of a communication API that exposes the communication services offered by the NoC to the application developer. Executing real and synthetic applications in two different MPSOCs, and using four different NoC communication services enabled to demonstrate the efficiency of the proposed approach to meet applications requirements.

Power efficient design of an amplifier using submicron technology

In an electronics circuit, a set of components named as modules or blocks are connected through ‘wires’ called as interconnects. Floorplanning and placement are used to reduce the total area, size, power, temperature and cost of any circuit design. Various computational techniques are used to calculate and minimise the above parameters. A single IC consists of number of processing elements (PEs), which works on various voltage ranges. This makes IC power consumption increase; thereby temperature of the chip also increases. The increased temperature positions in some parts are called as hot-spots. The main goal of this paper is to focus on calculation of area, power and hotspot of any complicated VLSI circuit and to show microwind simulation output for future design of any complicated circuits for various temperature ranges. The deep submicron technology is widely used for design of any analogue circuits in microwind.

Experimental Evaluation of the Performance of Processing Stealing Technique: A Scalable Load Balancing Technique for a Dynamic Multiprocessor System

paper reports preliminary experimental evaluation of a Processing Elements Stealing (PE-S) technique which was targeted as efficient and scalable load balancing technique for dynamically structured multiprocessor systems. The multiprocessor system is imagined as a dynamic cluster based multiprocessor. Each cluster of the multiprocessor system is a node in symmetric multiprocessor architecture and the number of Processing Element (PE) in each cluster is dynamically determined at runtime. The PE-S technique dynamically computes the configuration ratio using the number of threads in the dynamically assigned tasks to generate the new number of PE for each cluster. This new configuration ratio is thereafter used to balance the additional computational work generated by runtime instantiation of current workloads for each cluster. In this work, the efficiency of the PE-S was evaluated using memory traces of some tightly parallel applications where the amount of parallelism is parameterized. These traces were used as workloads on two different simulation setups; the first is a dynamic multiprocessor with PE-S while the other was also a dynamic multiprocessor but without PE-S. This is to evaluate the performance of the PE-S load balancing technique on the targeted multiprocessor. Also the efficiency of PE-S reconfigurations was compared with other possible reconfiguration ratios. The experimental results showed that the load balancing algorithm is efficient and scalable for balancing at least 100,000 instructions tasks and PE-S generated ratios are averagely better than any other reconfiguration ratios.

Dynamic tuning of the workload partition factor and the resource utilization in data-intensive applications

The recent data deluge needing to be processed represents one of the major challenges in the computational field. This fact led to the growth of specially-designed applications known as data-intensive applications. In general, in order to ease the parallel execution of data-intensive applications input data is divided into smaller data chunks that can be processed separately. However, in many cases, these applications show severe performance problems mainly due to the load imbalance, inefficient use of available resources, and improper data partition policies. In addition, the impact of these performance problems can depend on the dynamic behavior of the application.This work proposes a methodology to dynamically improve the performance of data-intensive applications based on: (i) adapting the size and the number of data partitions to reduce the overall execution time; and (ii) adapting the number of processing nodes to achieve an efficient execution. We propose to monitor the application behavior for each exploration (query) and use gathered data to dynamically tune the performance of the application. The methodology assumes that a single execution includes multiple related queries on the same partitioned workload.The adaptation of the workload partition factor is addressed through the definition of the initial size for the data chunks; the modification of the scheduling policy to send first data chunks with large processing times; dividing of the data chunks with the biggest associated computation times; and joining of data chunks with small computation times. The criteria for dividing or gathering chunks are based on the chunks’ associated execution time (average and standard deviation) and the number of processing elements being used. Additionally, the resources utilization is addressed through the dynamic evaluation of the application performance and the estimation and modification of the number of processing nodes that can be efficiently used.We have evaluated our strategy using as cases of study a real and a synthetic data-intensive application. Analytical expressions have been analyzed through simulation. Applying our methodology, we have obtained encouraging results reducing total execution times and efficient use of resources.

A hardware centric algorithm for the best matching unit searching stage of the SOM-based quantizer and its FPGA implementation

Parts of a self-organizing map (SOM)-based quantizer can be performed in parallel, i.e., distance calculation between an input pixel and a group of codewords or processing elements (PEs), and updating codewords. To search for the best matching unit (BMU) whose distance is the minimum, all distances are inevitably required to compare with each other. It is true that a group of comparators and registers can be instantiated with equal size to the distances (which is equivalent to the number of PEs) and performed in a multistage manner to come up with the minimum distance and its index. In this way, the algorithm requires n = log2C clock cycles, where C is the number of PEs and $$\sum\nolimits_{k=0}^{n-1}{2^k}$$?k=0n-12k are the number of comparators and registers. In this paper, we propose a novel hardware centric algorithm with the objective to accelerate the BMU searching stage of the SOM-based quantizer. In a simple form, the algorithm relies on using a PE's distance as an address of a memory to store its index. Simultaneously with storing indices of all PEs, the states of all `non-empty' addresses within the memory are prepared. In this way, it can be stated that the position of the first non-empty state corresponds to the memory address whose content is the BMU index. The approach to find the first position of the non-empty state within a single clock cycle is also detailed. The algorithm is also adapted to make it more feasible to realize on an FPGA platform. The synthesis results compared with the conventional BMU searching indicate that the FPGA resource requirements of the algorithm are 1.8 and 1.57 times in terms of slices and LUT usages, respectively. In terms of acceleration, the algorithm outperforms the conventional ones by a factor of 1.8 for a test image of size 512 × 512 pixels.

파장 라우팅 광학 네트워크-온-칩에서의 최소 개수 파장 할당 기법

실리콘 포토닉스 기반의 광학 네트워크-온-칩(Optical NoC, ONoC)은 차세대 엑사스케일 컴퓨팅(Exascale computing)을 위한 유망 아키텍처 기술 중 하나이다. 최근 들어 활발해지고 있는 ONoC의 연구들은 파장 분할 다중화(Wavelength Division Multiplexing, WDM)를 이용하여 대역폭을 더욱 향상시키고 광신호의 경로 충돌을 방지하는데 초점을 두고 있다. 하지만 기존 ONoC 연구에서는 중앙 집중형 라우터 구조 위주로 Processing Element(PE)의 수가 증가함에 따라 WDM을 위해 사용되는 파장 수가 선형적으로 증가한다. 이러한 파장 수의 증가는 다중 파장을 위한 광원 및 광학 스위치 등 광학 장치를 구성하기 위한 비용을 증가시키고 광신호의 상호 간섭에 의한 감쇄 효과 등으로 ONoC의 확장성을 제한한다.<BR> 본 논문에서는 WDM 기반 2D-mesh 구조의 ONoC를 위한 분산형 광학 라우팅 아키텍처를 제안하고 커뮤니케이션의 연결정도에 따라 필요한 파장 수를 최소화하는 방법을 제시하였다. 기존 중앙 집중형 라우팅 아키텍처와 비교하여 8x8 네트워크에서 평균 56% 파장 수와, 21%의 광학 스위치 수를 감소시켰다.

Exploiting fine-grain parallelism in the H.264 deblocking filter by operation reordering

In the H.264 video compression standard, the deblocking filtering contributes about one-third of all computation in the decoder. With many-core architectures becoming the future trend of system design, computation time can be reduced if the deblocking appropriately apportions its operations to multiple processing elements. In this study, we used a four-pixel-long boundary as the basis for analyzing and exploiting possible parallelism. Compared with the two-dimensional (2D) wavefront method order for deblocking both 1920×1080- and 1080×1920-pixel frames, the proposed design exhibits speedups of 1.92 and 2.44 times, respectively, given an unlimited number of processing elements. Compared with our previous design, it gains speedups of 1.25 and 1.13 times, respectively. In addition, as the frame size grows, this approach requires only extra time that is proportional to the square root of the frame size increase (keeping the same width to height ratio), pushing the boundary of practical real-time deblocking of increasingly larger video sizes.

An In-Place FFT Architecture for Real-Valued Signals

This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

A case for three‐dimensional stacking of tightly coupled data memories over multi‐core clusters using low‐latency interconnects

Shared tightly coupled data memories are key architectural elements for building multi-core clusters in programmable accelerators and embedded systems, as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of these memories largely depends on the architecture of the interconnect used between processing elements (PEs) and memory banks. The advent of three-dimensional (3D) technology has provided new opportunities to increase design modularity and reduce latency and manufacturing cost. In this study, the authors propose two 3D network architectures: C-logarithmic interconnect (LIN) and Distributed logarithmic interconnect (D-LIN) (designed in synthesisable RTL), which allow modular stacking of multiple L1 memory dies over a multi-core cluster with a limited number of PEs. The authors have used two through-silicon-via technologies: the state-of-the-art micro-bumps and the promising and dense Cu–Cu direct bonding. The overhead of electrostatic discharge protection circuits has been considered, as well. Architectural simulation results demonstrate that, in processor-to-L1-memory context, C-LIN and D-LIN perform significantly better than traditional network-on-chips and simple time-division multiplexing buses. Furthermore, post-layout results show that the proposed 3D architectures achieve comparable speed against their 2D counterparts, whereas enabling modularity: from 256 kB to 2 MB L1 memory configurations with a single mask set.

X-Network: An area-efficient and high-performance on-chip wormhole interconnect network

Packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future chip many-core processors and complex Systems on Chip (SoCs). However, the quest for high-performance networks has led to very area-consuming and complicated routers. Buffers consume a significant portion of the router area, but their utilization is very low most of the time. This paper presents a low-area and high-performance wormhole-switching NoC named X-Network that is built on a novel PE (Processing Element)-router organization. In X-Network, each router is shared by four PEs and each general PE has access to four directly-connected routers in addition to NEWS (North, East, West, South) connections between neighboring PEs. By sharing routers among PEs, the network reduces the average hop count for a packet thereby reducing the latency and improving the throughput of the network. Our design not only reduces the total number of routers for a given number of PEs, but also offers much more routing flexibility compared to existing mesh-based solutions. Extensive simulation results using both synthetic workloads and SPLASH-2 applications show that X-Network reduces the network latency by up to 50.3% for a system with 64 PEs. The network saturation point is extended by up to approximately 100% using the fully-adaptive routing algorithm. Our proposed hybrid buffer design can improve the performance by additional 22%.

Sharded Router: A novel on-chip router architecture employing bandwidth sharding and stealing

Abstract Packet-based networks-on-chip (NoC) are considered among the most viable candidates for the on-chip interconnection network of many-core chips. Unrelenting increases in the number of processing elements on a single chip die necessitate a scalable and efficient communication fabric. The resulting enlargement of the on-chip network size has been accompanied by an equivalent widening of the physical inter-router channels. However, the growing link bandwidth is not fully utilized, because the packet size is not always a multiple of the channel width. While slicing of the physical channel enhances link utilization, it incurs additional delay, because the number of flit per packet also increases. This paper proposes a novel router micro-architecture that employs fine-grained bandwidth “sharding” (i.e., partitioning) and stealing in order to mitigate the elevation in the zero-load latency caused by slicing. Consequently, the zero-load latency of the Sharded Router becomes identical with that of a conventional router, whereas its throughput is markedly improved by fully utilizing all available bandwidth. Detailed experiments using a full-system simulation framework indicate that the proposed router reduces the average network latency by up to 19% and the execution time of real multi-threaded workloads by up to 43%. Finally, hardware synthesis analysis verifies the modest area overhead of the Sharded Router over a conventional design.

Increasing the Throughput of Polar Decoders

The serial nature of successive-cancellation decoding results in low polar decoder throughput. In this letter we present an improved version of the simplified successive-cancellation decoding algorithm that increases decoding throughput without degrading the error-correction performance. We show that the proposed algorithm has up to three times the throughput of the simplified successive-cancellation decoding algorithm and up to twenty-nine times the throughput of a standard successive-cancellation decoder while using the same number of processing elements.

Parallel programming patterns for multi-processor SoC

Efficient, scalable and productive parallel programming is a major challenge for exploiting the future multi-processor SoC platforms. This article presents the MultiFlex programming environment which has been developed to address this challenge. It is targeted for use on Platform 2012 , a scalable multi-processor fabric. The MultiFlex environment supports high-level simulation, iterative platform mapping, and includes tools for programming model aware debug, trace, visualization and analysis. This article focuses on the two classes of programming abstractions supported in MultiFlex. The first is a set of Parallel Programming Patterns (PPP) which offer a rich set of programming abstractions for implementing efficient data- and task-level parallel applications. The second is a Reactive Task Management (RTM) abstraction, which offers a lightweight C-based API to support dynamic dispatching of small grain tasks on tightly coupled parallel processing resources. The use of the MultiFlex native programming model is illustrated through the capture and mapping of two representative video applications. The first is a high-quality rescaling (HQR) application on a multi-processor platform. We present the details of the optimization process which was required for mapping the HQR application, for which the reference code requires 350 GIPS (giga instructions per second), onto a 16 processor cluster. Our results show that the parallel implementation using the PPP model offers almost linear acceleration with respect to the number of processing elements. The second application is a high-definition VC-1 decoder. For this application, we illustrate two different parallel programming model variants, one using PPPs, the other based on RTM. These two versions are mapped onto two variants of a homogeneous version of the Platform 2012 multi-core fabric.

Estimating parallel performance

In this paper we introduce our estimation method for parallel execution times, based on identifying separate “parts” of the work done by parallel programs. Our run time analysis works without any source code inspection. The time of parallel program execution is expressed in terms of the sequential work and the parallel penalty. We measure these values for different problem sizes and numbers of processors and estimate them for unknown values in both dimensions using statistical methods. This allows us to predict parallel execution time for unknown inputs and non-available processor numbers with high precision. Our prediction methods require orders of magnitude less data points than existing approaches. We verified our approach on parallel machines ranging from a multicore computer to a peta-scale supercomputer.Another useful application of our formalism is a new measure of parallel program quality. We analyse the values for parallel penalty for both growing input size and for increasing numbers of processing elements. From these data, conclusions on parallel performance and scalability are drawn.

Performance Evaluation for Field Programmable Gate Array-based Bioinformatics Sequence Alignment

Sequence alignment is a computationally expensive activity in bioinformatics that can benefit significantly from Field Programmable Gate Array-based high-performance computing systems. This paper evaluates the performance of such systems for bioinformatics sequence alignment applications considering various parameters like data bus width (W), the number of processing elements, and the maximum operating frequency.

Exploration of Optimal Many-Core Models for Efficient Image Segmentation

Image segmentation plays a crucial role in numerous biomedical imaging applications, assisting clinicians or health care professionals with diagnosis of various diseases using scientific data. However, its high computational complexities require substantial amount of time and have limited their applicability. Research has thus focused on parallel processing models that support biomedical image segmentation. In this paper, we present analytical results of the design space exploration of many-core processors for efficient fuzzy c-means (FCM) clustering, which is widely used in many medical image segmentations. We quantitatively evaluate the impact of varying a number of processing elements (PEs) and an amount of local memory for a fixed image size on system performance and efficiency using architectural and workload simulations. Experimental results indicate that PEs=4,096 provides the most efficient operation for the FCM algorithm with four clusters, while PEs=1,024 and PEs=4,096 yield the highest area efficiency and energy efficiency, respectively, for three clusters.

High‐performance execution of service compositions: a multicore‐aware engine design

SUMMARYAlthough modern computer hardware offers an increasing number of processing elements organized in nonuniform memory access (NUMA) architectures, prevailing middleware engines for executing business processes, workflows, and Web service compositions have not been optimized for properly exploiting the abundant processing resources of such machines. Amongst others, factors limiting performance are inefficient thread scheduling by the operating system, which can result in suboptimal use of system memory and CPU caches, and sequential code sections that cannot take advantage of multiple available cores.In this article, we study the performance of the JOpera process execution engine on recent multicore machines. We first evaluate its performance without any dedicated optimization for multicore hardware, showing that additional cores do not significantly improve performance, although the engine has a multithreaded design. Therefore, we apply optimizations on the basis of replication together with an improved, hardware‐aware usage of the underlying resources such as NUMA nodes and CPU caches. Thanks to our optimizations, we achieve speedups from a factor of 2 up to a factor of 20 (depending on the target machine) when compared with a baseline execution ‘as is’. Copyright © 2012 John Wiley &amp; Sons, Ltd.