X-Network: An area-efficient and high-performance on-chip wormhole interconnect network

Abstract

Packet-switching networks on chip (NoCs) have emerged as a promising paradigm for designing scalable communication infrastructures for future chip many-core processors and complex Systems on Chip (SoCs). However, the quest for high-performance networks has led to very area-consuming and complicated routers. Buffers consume a significant portion of the router area, but their utilization is very low most of the time. This paper presents a low-area and high-performance wormhole-switching NoC named X-Network that is built on a novel PE (Processing Element)-router organization. In X-Network, each router is shared by four PEs and each general PE has access to four directly-connected routers in addition to NEWS (North, East, West, South) connections between neighboring PEs. By sharing routers among PEs, the network reduces the average hop count for a packet thereby reducing the latency and improving the throughput of the network. Our design not only reduces the total number of routers for a given number of PEs, but also offers much more routing flexibility compared to existing mesh-based solutions. Extensive simulation results using both synthetic workloads and SPLASH-2 applications show that X-Network reduces the network latency by up to 50.3% for a system with 64 PEs. The network saturation point is extended by up to approximately 100% using the fully-adaptive routing algorithm. Our proposed hybrid buffer design can improve the performance by additional 22%.