Number Of Latches Research Articles

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital‐to‐analogue converters

Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built-in memory to provide the required bit stream for one input bit of the DAC. This work presents a half-rate 32 GSps MUX with 1 kbit built-in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar-CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re-time the clock and data signals. At the highest rates, a multiphase-clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase-clock structure is enhanced in this work. At lower rates, a one-stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue–digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low-power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.

A modified MAP decoder architecture for low power consumption using folded technique

A modified MAP decoder architecture to reduce the power using folded technique is presented in this article. Firstly, the folded technique is applied in the interleaving and deinterleaving unit and then in the MAP decoder unit. The number of latches is reduced by using folded technique in the interleaving and deinterleaving unit. Here the end-to-end delay by using the proposed folded technique in the interleaving block is 2 M. But existing reports reveal that end-to-end delay is 2MN − 2 M + 2 for BI and M(N − 1) for FCI. In addition to the end-to-end delay, the number of latches is also reduced by using folded technique. We have used only M − 2 latches, whereas for other methods the number of latches utilised is more. The proposed MAP decoder reduce the memory elements up to 88% for the block interleaver, when M = NJ. In addition to that we achieved a memory element of 2 K −1 + 4 when calculating LLR by applying folded technique in the MAP decoder. Total power consumption is 160.3mW when folded technique is used in the interleaving block and the MAP decoder section. This ratio is less than the existing reported values for K = 5, code rate ½ and k = 4.

Retiming Pulsed-Latch Circuits With Regulating Pulse Width

A pulsed-latch is an ideal sequencing element for high-performance application-specific integrated circuit designs due to its simple timing model and reduced sequencing overhead. The possibility of time-borrowing while a latch is transparent is deliberately ignored in pulsed-latch circuits to simplify the timing model. However, using more than one pulse width allows another form of time-borrowing, which preserves the simple timing model. The associated problem of allocating pulse widths is called pulse width allocation (PWA); and we combine it with retiming to achieve a shorter clock period in pulsed-latch circuits than can be obtained by retiming or PWA alone, with less requirement for extra latches than standard retiming. An exact solution can be obtained by an integer linear programming, but this is restricted to small circuits. We therefore introduce a practical heuristic, which performs clock skew scheduling to find the minimum clock period and then brings the clock skew as nearly back to zero as possible by converting it to combined retiming and PWA. Experiments with 45 nm technology circuits suggest that the heuristic algorithm achieves a clock period that is close to minimum in most circuits, with an average 23% reduction compared to initial circuit, at an average cost of a 16% increase in the number of latches. On the same benchmarks, standard retiming achieves a 20% reduction in clock period with a 29% increase in the number of latches. The cost in extra area and energy is reasonable.

A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding

Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 µm CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45mm2, and yields a throughput rate of 20M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.

Modified asynchronous wave-pipelining

A modified asynchronous wave-pipelining design method for optimising circuit performance is presented. Using this method, the number of latches in the circuit can be decreased compared with the asynchronous wave-pipelined circuit that uses latches at every gate level. As a result, the latency of the circuit can be reduced drastically and the number of delay elements used in the wave-pipelined circuit can be decreased. To verify the proposed method, the authors have designed and 8/spl times/8 multiplier and performed simulations using HSPICE. The latency of the multiplier decreased by 40% when compared with the asynchronous wave-pipelined circuit and a delay latch replaced two delay elements that were used in the wave-pipelined circuit. The designed multiplier works well at 1 GHz.

Optimizing large multiphase level-clocked circuits

Retiming is a powerful technique for optimizing sequential circuits. The transparent nature of level sensitive latches enables level-clocked circuits to operate faster and require fewer memory elements than edge-triggered circuits. However, this transparency makes the operation of level-clocked circuits very complex, and optimization of level-clocked circuits is a difficult task. This work presents efficient algorithms for retiming large level-clocked circuits. To provide us with a simpler view of the operation of level-clocked circuits, we present the relationship between retiming and clock skew optimization. We then utilize this relationship to develop efficient retiming algorithms for period and area optimization. For period optimization, we present an algorithm which produces near-optimal results, but is significantly faster than the traditional algorithms. In this approach, we first calculate the best possible clock period and the amount of motion required for each latch. The latches are then relocated in an attempt to achieve this period. Area, as measured by the number of latches in the circuit can be optimized by solving a linear program. We apply efficient pruning techniques to reduce the size of this linear program, while preserving optimality. Since generating the linear program is a major part of the computational requirements of minarea retiming, we present techniques for efficient generation of the reduced linear program. This enables us to perform area optimization of large circuits clocked by symmetric multiphase clocks in very reasonable time, without sacrificing optimality. We present results on circuits with up to 56000 gates, performing period optimization in under 20 s and area optimization in under 1.5 h.

Efficient semisystolic architectures for finite-field arithmetic

Finite fields have been used for numerous applications including error-control coding and cryptography. The design of efficient multipliers, dividers, and exponentiators for finite field arithmetic is of great practical concern. In this paper, we explore and classify algorithms for finite field multiplication, squaring, and exponentiation into least significant bit first (LSB-first) scheme and most significant bit first (MSB-first) scheme, and implement these algorithms using semisystolic arrays. For finite field multiplication (for programmable as well as fixed field order) and exponentiation, we conclude that LSB-first algorithms are more efficient as their basic cells have less critical path computation time. Another advantage of LSB-first scheme is its capability of achieving substructure sharing among multiple operations, which could lead to savings in hardware when these arithmetic units are used as building blocks for a large system. For finite field squaring operation, it turns out that the MSB-first algorithm is more efficient as it leads to simpler architectures. Bit-level pipelined semisystolic architectures utilize broadcast signals. As a result, these require much less number of latches and lead to much smaller latency than the corresponding systolic array, with the same cycle time (the computation time in one basic cell). Efficient VLSI implementation of semisystolic multipliers, squarers and exponentiators are designed and compared with existing architectures. A novel architecture for computing AB/sup n/+C using power representation is also presented.

Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability

In this paper, we present methods for synthesis of sequential circuits for easy testability based on a scheme previously referred to as synthesis for parallel scan. A heuristic is used to achieve maximal merging of the testability logic with the normal combinational logic of the sequential circuit in order to minimize the area overhead. The latches used in the proposed scheme are normal nonscan latches. The synthesis for parallel scan scheme is applied to two different fault models. To facilitate stuck-at-fault testability of sequential circuits, the synthesis for parallel scan method is augmented with a novel structural analysis technique for selection of latches for partial scan with emphasis on minimization of delay overhead. Experimental results on ISCAS '89 benchmarks resynthesized by our method indicate that one can, in general, achieve the same level of testability with less area and delay overheads, as compared to the conventional structural analysis method for partial scan. A method for synthesizing fully hazard-free robust path-delay fault testable sequential circuits using the concept of synthesis for parallel scan is also presented. When the number of primary inputs of the sequential circuit is at least as large as the number of latches, only normal nonscan latches are required. Experimental results on MCNC and ISCAS '89 benchmarks show the area overheads to be very reasonable. No previous method could ensure complete robust testability of all path-delay faults in a sequential circuit without assuming a completely enhanced scan, even under the above condition. However, when this condition is not met, i.e., the number of primary inputs is less than the number of latches, we introduce the concept of synthesis for maximally parallel enhanced scan. This still provides complete robust testability, however, at the expense of a higher area overhead.

Automated verification of behavioral equivalence for microprocessors

Presents a new method for verifying, in a fully automated way, that two synchronous sequential circuits have the same input/output behavior. The method applies to designs in which a distinction between data path and control can be made, and in particular to microprocessors. The verification is carried out at the register-transfer level. In contrast with previous methods, our procedure is not limited by the total number of latches in the circuit: it runs in time that is independent of the width of the data path. A price has to be paid for this: the procedure does not always terminate, and may produce false negatives. We argue, however, that these problems should not come up when verifying general purpose microprocessors. We have implemented the procedure in Prolog on an IBM RS/6000 workstation, and have tried it on the Tamarack-3 microprocessor previously verified by J.J. Joyce (1990) with the interactive theorem prover HOL at the University of Cambridge. We have verified the equivalence of several alternative implementations to the original one, in times ranging from 11 to 26 s, and we have detected the errors in several incorrect implementations, in times ranging from 1 to 26 s. >

Pipelined serial/parallel multiplier with contraflowing data streams

An improved architecture of the Muller pipeline serialparallel multiplier is presented. The proposed solution is based on the integration of two Muller cells into one. This modification has resulted in a reduction of the number of latches by 25% and an increase in the effectiveness of the architecture by eliminating interspersed zeros in the input data streams. An area×time criteria is used to compare the modified architecture with the Muller multiplier.

Design for test using partial parallel scan

Traditional scan design techniques such as level-sensitive scan design, scan path, and random-access scan suffer from the drawback that the extra test application effort (which includes both time and memory) required is directly proportional to the number of latches and can become quite significant. A scan design technique termed partial parallel scan which reduces test application effort by one to two orders of magnitude is presented. Theoretical and practical aspects of the design method are discussed. The practical use of the partial parallel scan technique has been demonstrated with an LSI circuit and a VLSI circuit designed using silicon compiler tools. >

Invited paper Data rate optimization in synchronous circuits

Abstract Since the data rate of a synchronous circuit is proportional to the reciprocal of its clock period, it is desirable to shorten the clock period for a better throughput. In this paper, we develop a method to reschedule any designed synchronous circuit into one with preassigned clock period. The numbers of latches between the connected function elements are properly adjusted and their total number is kept as small as possible.