Abstract
A modified asynchronous wave-pipelining design method for optimising circuit performance is presented. Using this method, the number of latches in the circuit can be decreased compared with the asynchronous wave-pipelined circuit that uses latches at every gate level. As a result, the latency of the circuit can be reduced drastically and the number of delay elements used in the wave-pipelined circuit can be decreased. To verify the proposed method, the authors have designed and 8/spl times/8 multiplier and performed simulations using HSPICE. The latency of the multiplier decreased by 40% when compared with the asynchronous wave-pipelined circuit and a delay latch replaced two delay elements that were used in the wave-pipelined circuit. The designed multiplier works well at 1 GHz.
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