Number Of Garbage Outputs Research Articles

Advancing nanoscale computing: Efficient reversible ALU in quantum-dot cellular automata

This paper presents a significant contribution to the field of nanoscale computing by proposing an innovative reversible Arithmetic and Logic Unit (ALU) implemented in Quantum-Dot Cellular Automata (QCA). Reversible logic and QCA technology offer promising alternatives to conventional CMOS technology, addressing the challenges of operating at nanoscale dimensions. The primary objective is to develop a highly efficient ALU capable of performing 26 distinct arithmetic and logical operations. The ALU design is based on a novel reversible full adder-subtractor optimized for minimal quantum cost, which is crucial for energy-efficient quantum computation. The evaluation encompasses various criteria related to reversibility, such as gate count, number of constant inputs, number of garbage outputs, and quantum cost. QCA-specific criteria, including cell count, occupied area, and clock cycles, are also considered. The outcomes of this research contribute to the advancement of cell-efficient nanoscale computing, with implications for quantum computation, emerging technologies, and future integrated circuit design.

Optimized Design of Decoder 2 to 4, 3 to 8 and n to 2n using Reversible Gates

The design of low consumption CMOS circuits, nanotechnologies and quantum computing has becomed more attached to the reversible logic. A set of gates have been recently exploited in reversible computer science for the design of certain circuits. Among them, we find the decoders. In this paper we have exploited a recent study making the design of the decoder 2 to 4, 3 to 8, and n to 2n, our work aims to enhance the previous designs , by replacing some reversible gates by others while maintaining their functionality and improving their performance criteria namely the number of gates (CG), number of garbage outputs (NGO), number of constant inputs(NCI), Quantum cost (QC) and hardware complexity (HC), compared to our study of the base and other recent studies from which we have obtained remarkable results.

Toward novel designs of reversible ternary 6:2 Compressor using efficient reversible ternary full-adders

Integrated circuits always face with two major challenges including heat caused by energy losses and the area occupied. In recent years, different strategies have been presented to reduce these two major challenges. The implementations of circuits in a reversible manner as well as the use of multiple-valued logic are among the most successful strategies. Reversible circuits reduce energy loss and ultimately eliminate the problem of overheating in circuits. Preferring multiple-valued logic over binary logic can also greatly reduce area occupied of circuits. When switching from binary logic to multiple-valued logic, the dominant thought in binary logic is the basis of designing computational circuits in multiple-valued logic, and disregards the capabilities of multiple-valued logic. This can cause a minimal use of multiple-valued logic capabilities, increase complexity and delay in the multiple-valued computational circuits. In this paper, we first introduce an efficient reversible ternary half-adder. Afterward, using the reversible ternary half-adder, we introduce two reversible versions of traditional and comprehensive reversible ternary full-adders. Finally, using the introduced reversible ternary full-adders, we propose two novel designs of reversible ternary 6:2 Compressor. The results of the comparisons show that although the proposed circuits are similar to or better than previous corresponding designs in terms of criteria number of constant input and number of garbage outputs, they are superior in criterion quantum cost.

A Review: Asynchronous Counters Using Quantum Gates

The major trouble at present time technology is the information loss due to high technology circuits and system designed using irreversible hardware, to solve this problem used quantum gate. The prime purposed of designing quantum gate to reduce power consumption, decrease quantum cost, delay, number of garbage outputs. Quantum gate requires non-demolition of information, Therefore the number of inputs must be similar to the number of outputs. This paper presents a review of the asynchronous counter designed by T flip-flop and comparing with existing.

A new design of a low-power reversible Vedic multiplier

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

Towards designing quantum reversible 32-bit MIPS register file

Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

Towards designing quantum reversible 32-bit MIPS register file

Reversible circuit design can be applied in various emerging technologies such as quantum computing. Since researchers have proposed many building blocks and designed small circuits (e.g., reversible full adder) already, it is the time to design large-scale reversible circuits. This paper proposes a novel quantum reversible 32-bit MIPS register file for quantum computer processors. It presents a reversible 5-to-32 decoder, 32 reversible buffer registers, and two reversible 32-to-1 multiplexers, too. The proposed reversible decoder block, namely GH-DEC, and the proposed reversible multiplexer block, namely GH-MUX, use the Feynman, Toffoli, and Fredkin gates. They have been designed by a minimum number of constant inputs, number of garbage outputs, and quantum cost. Besides, output expressions of all the circuits are simplified to enhance the performance of proposed quantum design, considerably. Comparison results show that the proposed reversible design surpasses the existing works in terms of the number of constant inputs, number of garbage outputs, and quantum cost.

Efficient design of quaternary quantum comparator with only a single ancillary input

Circuit design with no energy dissipation is possible in the reversible logic. Also, using the quantum multiple-valued logic in the design of circuits due to the reduction of circuit width leads to the smaller chip area and lower power consumption. Quaternary reversible logic potentially has several advantages in comparison to the equivalent ternary and binary quantum technologies. Hence, the quaternary quantum technology is a promising choice for the future digital system design. Here, the authors proposed an efficient design of 1-qudit and n -qudit quantum comparators. The comparator module is widely used in search conditions, such as Grover's quantum search algorithm in quantum computing. The proposed circuits were better than their existing counterparts in terms of quantum cost, the number of constant inputs, the number of garbage outputs, and hardware complexity. To design these circuits, they have used 1-qudit gates and 2-qudit Muthukrishnan-Stroud gates. The efficiency of their proposed circuits was reported.

Low-cost and compact design method for reversible sequential circuits

Reversible logic plays an important role in nanotechnology-based systems; therefore, it has become an interesting topic for many researchers in this field. Although many researchers are investigating techniques to synthesize reversible combinational logic, few are working in the field of reversible sequential logic. The traditional method to design a sequential circuit is a replacement technique. In this technique, in order to design a reversible sequential circuit, all parts of an irreversible design (e.g., latches and flip-flops and associated combinational gates) are replaced by their reversible counter parts, which leads to circuits with high quantum cost. In this paper, we propose a direct and compact design of reversible synchronous sequential circuits. The EXOR of Products of EXOR (EPOE) expressions are applied, to reduce the quantum cost of sequential logic circuits. We present designs for some practical sequential circuits, such as state machines, counters and shift registers. To show the efficiency of the proposed method, we have designed a proof of concept of our designs to design a practical sequential system: a reversible self-controlled serial adder. Our designs considerably reduce performance cost factors: including quantum cost, number of constant inputs or the number of garbage outputs and delay.

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

A Novel Nanometric Parity-Preserving Reversible Carry-Lookahead Adder

ABSTRACTDuring recent years, reversible logic received important attention in cryptography, optical processing, quantum computing, and nanotechnology. Among the reversible computation units, the adder unit is considered the most fundamental computation unit to build a quantum computing system. Due to its low latency, the reversible carry-lookahead adder is mostly used and considered. Parity preserving is also one of the oldest methods for error recognition in digital systems. In this article, we offer new proposals for the nanometric parity-preserving reversible 2-bit carry-lookahead adder. Compared with previous designs, we will demonstrate that our designs would be optimal in the number of garbage outputs, constant inputs, and quantum costs. In order to design circuits at a higher level, we also offer new proposals for the nanometric parity-preserving reversible 4-bit carry-lookahead adder. Since previous proposals that were presented as 4-bit did not have the reversible parity-preserving property, we proceeded with our research.

Implementation and Analysis of Reversible logic Based Arithmetic Logic Unit

There is a tremendous growth in fabrication from small scale integration (SSI) to giant scale integration (GSI). It however raises a question of sustainability of Moore's law due to almost intolerable levels of power consumption. Researchers have invented a lot of methods to reduce power consumption and recent technologies are switching to reversible logic. Reversible logic has various applications in fields of computer graphics, optical information processing, quantum computing, DNA computing, ultra low power CMOS design and communication. Arithmetic Logic Unit (ALU) is considered to be the basic building block of a CPU in the computing environment and portability in computing system highly demands reversible logic based ALU. Modern processors usually have a word length of 32 or 64 bits. Divide and conquer approach principle cascades n number of 1 bit ALU to implement n bit ALU. Several researchers have proposed 1-bit ALU design using various reversible logic gates. This paper aims at categorizing various ways of implementation in VHDL using Xilinx ISE design suit 14.2 tool and comparative analysis of existing 1 bit ALU designs in terms of optimization metrics like power consumption, number of gates, number of constant inputs, number of garbage outputs and quantum cost. ALU realized using carry save adder block is found to be most optimum design in terms of gate count and quantum cost.

A new DFT methodology for k-CNOT reversible circuits and its implementation using quantum-dot cellular automata

Testable design of reversible circuits leads to a large increment in operating costs from their original circuits. This paper presents a new cost efficient methodology of converting k-CNOT gates based circuits into respective parity preserving circuits. The testability of these circuits can be achieved simply by checking the input and output parity by means of CNOT gates. The design process requires only a single wire for its formulation without an increase in number of garbage outputs and provides full fault coverage under single bit fault detection with lesser design complexity. Experiments were performed on a set of benchmark circuits and the results show a reduction in operating costs up to 45% as compared to prior work. The work is also justified by implementing k-CNOT gates in quantum-dot cellular automata (QCA) to prove the efficiency of our work in physical foreground.

A Power-Efficient Multiplexer using Reversible Logic

The basic concept of reversible circuits is to save energy dissipation in the form of both power and heat in lieu of some additional circuitry. Its use leads to compensating for the garbage bits that will be necessarily generated. Designing a multiplexer can prove to be a very useful block in many complex circuits. A Fredkin gate based multiplexer has been proposed for 180nm, 90nm and 45nm channel lengths. The designed circuit is expected to be fault-tolerant. The W/L ratio has been varied to find the least possible value of power dissipation of the circuit. Substrate-bias voltage of MOSFET can be varied in order to change the threshold voltage value of transistor which helps us in finding the optimum values of driving voltage, input voltage and substrate to bias voltage. Its use is most prominent in an inverter block where tenfold decrease is observed in bulk-driven supply compared to conventional CMOS technology. The value of the bias voltage is found out to be increasing for decreasing channel lengths but bulk-driven voltage supply is not useful in 45nm technology because of increase in transconductance owing to its fixed minimum (W/L) ratio. Delay and power-delay product are also important parameters that have been taken into account. Other important figures of merit like quantum cost, number of garbage outputs, number of gates and quantum depth have also been studied. All the simulations have been done on Cadence tool.

On Design of Parity Preserving Reversible Adder Circuits

In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.

Design and Implementation of High-Speed Low Power Multipliers Using Reversible Logic

Reversible logic is one of the promising research areas in low power applications such as quantum computing, optical information processing, DNA computing and also thermodynamic technology, Nanotechnology and low power CMOS design. In this paper, a novel Reversible logic gate has been proposed and novel architecture for multiplier is constructed by using ANU gate and PERES gate. A Multiplier is one of the key hardware blocks in most fast processing system which is not only a high delay block but also a major source of power dissipation. Power dissipation for Reversible logic gates is very less because of its reversibility property. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The primary characteristics like garbage outputs, Constant inputs and number of gates got decreased. The logical calculations also got decreased.

Reversible Logic Synthesis of Sequential Circuits

Reversible logic is gaining importance in recent years largely due to its property of low power consumption. It has a wide range of applications which include advance computing, low power CMOS, optical information processing, quantum computing, DNA cryptography and nanotechnology. Reversible gates are the building blocks of quantum computation. This paper presents a novel design of D, JK and T flip-flops using the existing reversible gates. All circuits have been modeled and verified using Verilog and Modelsim. A comparative study in terms of the number of gates, number of garbage outputs and quantum costs is also presented. General Terms Reversible logic, Quantum Cost, Reversible Gates, Sequential Circuits.

A Novel 4×4 Universal Reversible Gate as a Cost Efficient Full Adder/Subtractor in Terms of Reversible and Quantum Metrics

This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.

Novel Nanometric Reversible Low Power Bidirectional Universal Logarithmic Barrel Shifter with Overflow and Zero Flags

One of the most important issues in designing VLSI circuits is power consumption. Reversible logic which is widely utilized in quantum computing, low power CMOS design, optical information processing, bioinformatics and nanotechnology-based systems decreases power loss. A reversible circuit has zero internal power dissipation because it does not lose information. Reversible barrel shifters are required to construct reversible embedded digital signal and general-purpose processors. Data shifting is often used in high-speed/low-power error-control applications, floating point normalization, address decoding and bit indexing. This paper proposes a novel reversible bidirectional universal barrel shifter which is applied in high speed and high performance applications. The proposed barrel shifter is designed in a single circuit with overflow and zero flags. It performs three operations consisting of rotating, logical and arithmetic shifting that transfers and shifts data in both directions. The design is evaluated and formulated in terms of number of garbage outputs, number of constant inputs, quantum cost, number of reversible gates and hardware complexity. All the scales are in nanometric area.