A new DFT methodology for k-CNOT reversible circuits and its implementation using quantum-dot cellular automata

Abstract

Testable design of reversible circuits leads to a large increment in operating costs from their original circuits. This paper presents a new cost efficient methodology of converting k-CNOT gates based circuits into respective parity preserving circuits. The testability of these circuits can be achieved simply by checking the input and output parity by means of CNOT gates. The design process requires only a single wire for its formulation without an increase in number of garbage outputs and provides full fault coverage under single bit fault detection with lesser design complexity. Experiments were performed on a set of benchmark circuits and the results show a reduction in operating costs up to 45% as compared to prior work. The work is also justified by implementing k-CNOT gates in quantum-dot cellular automata (QCA) to prove the efficiency of our work in physical foreground.