Number Of Delay Elements Research Articles

QuCTS—Single-Flux Quantum Clock Tree Synthesis

Superconductive rapid single-flux quantum (RSFQ) is an emerging cryogenic technology, promising a significant boost in performance and ultralow power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS—single-flux Quantum (SFQ) Clock Tree Synthesis—is presented. QuCTS utilizes a two-stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1049 clock sinks in 53 min while satisfying the clock arrival time.

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.

Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry

This paper proposes an efficient structure for implementing a linear-phase finite-impulse-response (FIR) filter of an arbitrary order <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$N$</tex></formula> for the sampling-rate conversion by a rational factor of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L/M$</tex> </formula> , where <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L(M)$</tex> </formula> is the integer upsampling (downsampling) factor to be performed before (after) the actual filter. In this implementation, the coefficient symmetry of the linear-phase filter is exploited as much as possible and the number of delay elements is kept as low as possible while utilizing the following facts. When increasing (decreasing) the sampling rate by a factor of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L(M)$</tex></formula> , only every <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L$</tex></formula> th input sample has a nonzero value (only every <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$M$</tex> </formula> th output sample has to be evaluated). In this way, the number of required multiplications per output sample is reduced approximately by a factor of two compared with the conventional polyphase implementation. The proposed implementation is first illustrated using two examples. Based on these examples, guidelines are then given on how to efficiently realize an <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$N$</tex></formula> th-order linear-phase FIR filter for a sampling-rate converter having an arbitrary rational conversion factor <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L/M$</tex></formula> . Finally, the implementation complexity of the proposed approach is evaluated and some examples are included, showing the efficiency of the proposed implementation compared with other existing ones.

A Class of Wide-Band Linear-Phase FIR Differentiators Using a Two-Rate Approach and the Frequency-Response Masking Technique

This paper introduces a class of wide-band linear-phase finite-length impulse response (FIR) differentiators. It is based on two-rate and frequency-response masking techniques. It is shown how to use these techniques to obtain all four types of linear-phase FIR differentiators. Design examples demonstrate that differentiators in this class can achieve substantial savings in arithmetic complexity in comparison with conventional direct-form linear-phase FIR differentiators. The savings achievable depend on the bandwidth and increase with increasing bandwidth beyond the break-even points which are in the neighborhood of 90% (80%) of the whole bandwidth for Type II and III (Type I and IV) differentiators. The price to pay for the savings is a moderate increase in the delay and number of delay elements. Further, in terms of structural arithmetic operations, the proposed filters are comparable to filters based on piecewise-polynomial impulse responses. The advantage of the proposed filters is that they can be implemented using non-recursive structures as opposed to the polynomial-based filters which are implemented with recursive structures.

Improved delay-line based digital PWM for DC-DC converters

An improved delay-line based digital pulse-width modulator (DPWM) architecture for DC-DC converters is presented to significantly enhance the area and power efficiency. In order to reuse the delay elements, the proposed scheme utilises the rising delay and falling delay to achieve the coarse and fine resolution of the DPWM, respectively. An 8-bit DPWM employing the improved architecture was implemented in SMIC standard 0.13 µm CMOS process. Simulation results indicate that a 90% of size saving is achieved for 8-bit resolution compared to the conventional method. Owing to the decrease in the number of delay elements, power consumption is also reduced.

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

On the Arbitrary-Length $M$-Channel Linear Phase Perfect Reconstruction Filter Banks

This correspondence extends the theory and lattice factorizations for M-channel linear phase perfect reconstruction filter banks (LPPRFBs). We deal with FIR FBs with real-valued filter coefficients in which all filters have the same arbitrary length L = KM + beta (0 les beta < M) and same symmetry center, in contrast to traditional constrained length profile L=KM. First, refined existence conditions on this larger class of FBs are given. Then, lattice structures are developed for both odd and even-channel FBs, and their relationship with time-domain lapped transforms is explained. These structures are more general compared to conventional design methods, and cover them as special cases. Furthermore, we discuss how to structurally impose the regularity onto the lattice structure to ensure the smoothness of the basis function, which is very desirable in high performance image compression. Finally, these lattice structures are proven to be minimal in terms of the number of delay elements used in implementation, and to completely span the class of LPPRFBs with length L les 2M and the whole class of linear phase paraunitary filter banks (LPPUFBs).

A novel encoder/decoder design scheme utilizing differential detection in OCDMA systems

In this paper, we report the use of differential detection in optical code-division multiple access (OCDMA) systems which use encoders and decoders based on unbalanced codes and utilize bipolar modulation/differential detection to demonstrate a significant improvement in system performance. Differential detection has been reported earlier also requiring a large number of one-chips in the code for (balanced codes) or with unbalanced codes with very long temporal dimensions requiring a large number of delay elements (either the delay lines in the ladder-type structures or the gratings in the multiple fiber gratings) making the encoder/decoder structures. We use single pulse per row codes to design our system and carry out the simulations for showing the results. The improved BER performance is achieved that can be traded for increasing the number of codes. Using optical simulation tool, the OCDMA system has been simulated for four users. The results of this system utilizing differential detection and another system that uses the same coding scheme but employing direct detection, for the same number of interfering users, are shown for comparison. The BER and the power penalty plots are shown for the two systems. Also, it is shown that performance degradation occurs due to the linear and non-linear effects of the fiber medium. The BER worsens more rapidly with link length for direct detection case, whereas for differential detection with an initial improvement of 8 dB, the increase in BER is insignificantly small for a link length of 500 km.

The construction of periodically time‐variant convolutional codes using binary linear block codes

AbstractIn 1996 Rosenthal and York proposed (time‐invariant) BCH convolutional codes [4] in which the parity check matrix of a BCH code is used in the construction of the convolutional code. The lower bound on the minimum free distance of a BCH convolutional code is guaranteed by the BCH limit. In this paper we propose a periodically time‐variant convolutional code that can be constructed not only using the BCH parity check matrix but using the check matrix of any binary linear block code and show that the lower bound on the minimum free distance is guaranteed by the minimum free distance of the binary linear block code. In addition, taking 12 binary linear block codes as examples, we perform comparisons of the proposed codes with BCH convolutional codes using three evaluation criteria (minimum free distance, number of delay elements, coding rate) and show that there exist proposed codes that are superior to existing ones. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(9): 31– 40, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20271

On Simplified Order-One Factorizations of Paraunitary Filterbanks

This paper revisits the order-one factorization of causal finite impulse response (FIR) paraunitary filterbanks (PU FBs). The basic form of the factorization was proposed by Vaidyanathan et al. in 1987, which is a cascade of general unitary matrices separated by diagonal delay matrices with arbitrary number of delay elements. Recently, Gao et al. have proved the completeness of this factorization and developed a more efficient structure that only uses approximately half number of free parameters. In this paper, by briefly analyzing Gao et al.'s derivation, we first point out that Gao et al.'s factorization contains redundant free parameters. Two simplified structures of Vaidyanathan's factorization are then developed, i.e., a post-filtering-based structure and a prefiltering-based structure. Our simplification relies on consecutive removal of extra degrees of freedom in adjacent stages, which is accomplished through the C-S decomposition of a general unitary matrix. Since the conventional C-S decomposition leads to a redundant representation, a new C-S decomposition is developed to minimize the number of free parameters by further incorporating the Givens rotation factorization. The proposed structures can maintain the completeness and the minimality of the original lattice. Compared with Gao et al.'s factorization, our derivations are much simpler, while the resulting structures contain fewer free parameters and less implementation cost. Besides, these new factorizations indicate that for a PU FB with a given filter length, the symmetric-delay factorization offers the largest degrees of design freedom. Several design examples are presented to confirm the validity of the theory.

FPGA Implementation of Digital Filters Synthesized Using the FRM Technique

The effective length of a filter designed using the frequency-response masking (FRM) technique is very long and requires a very large number of delay elements. In this paper, we present some useful techniques for reducing the data transfer between the field programmable gate array (FPGA) and external memory when the random logic is implemented using the FPGA and the delay elements are implemented using an external memory such as dynamic random access memory.

Error Spectrum Shaping in Two‐Dimensional Separable‐Denominator Digital Filters

AbstractIn the implementation of recursive digital filters, the characteristics might be degraded due to finite word length effects. The degradation generates noise at the filter output which is caused by roundoff errors in the product quantization. A technique called error spectrum shaping (ESS) can be applied to suppress the noise. ESS usually relies on the use of feedback of roundoff errors and sometimes their feedforward. In this paper, a technique is developed for ESS in two‐dimensional separable‐denominator digital filters by applying both feedback and feedforward of roundoff errors. A two‐dimensional separable denominator is implemented with the minimum number of delay elements and includes two quantizers. A genetic algorithm is also applied to obtain the suboptimal discrete solution of feedback–feedforward coefficients for the purpose of cost reduction. Finally, a numerical example is given to illustrate the utility of the proposed technique. © 2001 Scripta Technica, Electron Comm Jpn Pt 3, 85(4): 10–19, 2002

Encoder and Distance Properties of Woven Convolutional Codes with One Tailbiting Component Code

Woven convolutional codes with one tailbiting component code are studied and their generator matrices are given. It is shown that, if the constituent encoders are identical, a woven convolutional encoder with an outer convolutional warp and one inner tailbiting encoder (WIT) generates the same code as a woven convolutional encoder with one outer tailbiting encoder and an inner convolutional warp (WOT). However, for rate Rtb < 1 tailbiting encoders, the WOT cannot be an encoder realization with a minimum number of delay elements. Lower bounds on the free distance and active distances of woven convolutional codes with a tailbiting component code are given. These bounds are equal to those for woven codes consisting exclusively of unterminated convolutional codes. However, for woven convolutional codes with one tailbiting component code, the conditions for the bounds to hold are less strict.

2-D lattice discrete filters: minimal delay and state space realization

A circuit realization is presented for two-dimensional (2-D) lattice discrete filters. The number of delay elements is minimal. Based on this circuit realization, the corresponding state space realization is derived. The matrices A, b, c', and the scalar d of the 2-D state space model are presented in generalized form. The dimension of the 2-D state space vector is minimal, and the corresponding transfer function is characterized by the all-pass property.

Generalized one-multiplier lattice discrete 2-D filters: minimal circuit and state-space realization

A circuit realization is presented for generalized one-multiplier lattice discrete two-dimensional (2-D) filters. The proposed structure has a minimum number of delay elements and multipliers. Based on this circuit realization, the corresponding state-space realization-representation is derived. The dimension of the 2-D state-space vector is minimal and the corresponding transfer function is characterized by the all-pass property.

An innovative linear response time-to-digital converter with a branched propagation delay chain

Utilizing the propagation delay in a chain of logic elements to digitize short time intervals has a high potential in various applications because the method has an ultrashort measurement “dead time” and its complete timing circuit can be easily integrated in a single semiconductor chip. However, the existing single-lined chain suffers from serious nonlinearity due to the longer path lengths at the foldings which are unavoidable when the number of delay elements is large as high time resolution requires. We propose a new configuration in which the delay chain is branched. The delay elements of each branch evenly subdivide the corresponding larger folding path so all units have the same delay time. The proposed time-to-digital converter with an 81-delay-unit branched chain and a built-in calibration circuit has been implemented on a commercial programmable logic device. It is used to interpolate different time durations within the 100 ns period of a standard 10 MHz clock. The digital time deviates less than 0.3 ns throughout the entire range. A similar single-lined delay chain, constructed for comparison, exhibits timing error up to 32.7 ns. A major improvement in linearity has been achieved by our device.

Modified asynchronous wave-pipelining

A modified asynchronous wave-pipelining design method for optimising circuit performance is presented. Using this method, the number of latches in the circuit can be decreased compared with the asynchronous wave-pipelined circuit that uses latches at every gate level. As a result, the latency of the circuit can be reduced drastically and the number of delay elements used in the wave-pipelined circuit can be decreased. To verify the proposed method, the authors have designed and 8/spl times/8 multiplier and performed simulations using HSPICE. The latency of the multiplier decreased by 40% when compared with the asynchronous wave-pipelined circuit and a delay latch replaced two delay elements that were used in the wave-pipelined circuit. The designed multiplier works well at 1 GHz.

Realization of Multidimensional Digital Transfer Functionswith Separable Numerator or Denominator Polynomials

In this paper a straightforward z-domain procedure for realizing multidimensional transfer functions with either numerator or denominator polynomial separable is presented. This procedure yields structures with minimum number of multipliers. It is shown that the number of delay elements can be reduced by selecting the optimum values for certain parameters. To facilitate this theorems that are applicable for some special cases are presented.

Two-dimensional B-CFE: Circuit and state space realization

In this paper the problem of the minimal circuit and state space realization for two-dimensional systems that can be expanded into B-type continued fractions, is considered. The matrix vectors A,b,c', having minimal dimension, and the scalar d of the Givone-Roesser state space model are derived. In addition, the corresponding circuit implementation of the system, with minimum number of delay elements, is given.

An application of a constrained adaptive lattice-structure allpass-based notch filter for advanced control of surface-mounted permanent-magnet synchronous drives

A constrained adaptive lattice-structure allpass-based notch filter provides minimal phase delay and complete attenuation of the notch frequency. The allpass sections of the filter are realized as structurally lossless bounded real functions, with a minimum number of delay elements and multipliers. The filter structure admits orthogonal tuning of the notch frequency and notch bandwidth. An improved control scheme for surface-mounted permanent-magnet synchronous (SMPMS) drives ensures stable high-performance operation in the Bur weakening region, utilizing the over-modulation and six-step modes of the space vector modulation (SVM). An automatic transition into the flux weakening region is achieved by controlling the reference voltage magnitude. The fifth and seventh stator current harmonics of the fundamental frequency, generated in the over-modulation and six-step modes, propagate through the current control loops, resulting in the sixth harmonic in the reference voltage for the flux weakening loop and deteriorating drive performance. To properly filter the sixth harmonic over the extended speed range of the drive, the constrained adaptive lattice-structure allpass-based notch filter is employed.