Number Of Clock Cycles Research Articles

Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures

Emulation of one architecture on another is useful when the architecture is under design, when software must be ported to a new platform or is being developed for systems which are still under development, or for embedded systems that insufficient resources to support the software development process. Emulation using an interpreter is typically slower than normal execution by up to 3 orders of magnitude. Our approach instead translates the program from the original architecture to another architecture while faithfully preserving its semantics at the lowest level. The emulation speeds are comparable to, and often faster than, programs running on the original architecture. Partial evaluation of architectural features is used to achieve such impressive performance, while permitting accurate statistics collection. Accuracy is at the level of the number of clock cycles spent executing each instruction (hence the description cycle-accurate ).

Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs

A novel mechanism that flexibly adapts data flows and configures computational units is proposed to establish an application-specific data path in the digital signal processor (DSP) that can efficiently perform multistandard video codecs. Based on this mechanism, the proposed application-specific data path, using the very long instruction word (VLIW) architecture with eight computational units of five arithmetic logic units (ALUs), one multiplier and two load/store units, is designed to perform five adaptive operations according to the characteristics of the low-level functions of MPEG-2, MPEG-4 and H.264/AVC video codecs. Using these adaptive operations, the proposed application-specific data path reduces the number of clock cycles required by the TI TMS320C64x data path to perform the low-level functions of the MPEG-2 video encoder and the H.264/AVC video decoder by 23.10% and 28.43%, respectively, for 30 352times288-pixel Foreman frames. Additionally, considering the operating frequency, the proposed application-specific data path reduces the computation time required by the TI TMS320C64x data path to realize the abovementioned encoder and decoder by 19.86% and 25.41%, respectively. Based on the TSMC 0.18-mum CMOS cell library, the proposed application-specific data path is implemented, and exhibits the highest ratio of computational power to hardware cost among all of the data paths associated with the conventional DSPs in implementing the low-level functions of video codecs

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory

This paper presents a scalable FPGA/ASIC implementation architecture for high-speed parallel table-lookup-coding using multi-ported content addressable memory, aiming at facilitating effective table-lookup-coding solutions. The multi-ported CAM adopts a Flexible Multi-ported Content Addressable Memory (FMCAM) technology, which represents an effective parallel processing architecture and was previously reported in [1]. To achieve a high-speed parallel table-lookup-coding solution, FMCAM is improved by additional schemes for a single search mode and counting value setting mode, so that it permits fast parallel table-lookup-coding operations. Evaluation results for Huffman encoding within the JPEG application show that a synthesized semi-custom ASIC implementation of the proposed architecture can already reduce the required clock-cycle number by 93% in comparison to a conventional DSP. Furthermore, the performance per area unit, measured in MOPS/mm2, can be improved by a factor of 3.8 in comparison to parallel operated DSPs. Consequently, the proposed architecture is very suitable for FPGA/ASIC implementation, and is a promising solution for small area integrated realization of real-time table-lookup-coding applications.

Improved$n$-Detection Test Sequences Under Transparent Scan

The quality of test sequences for scan circuits under a test-application scheme called transparent scan as n-detection test sequences is studied. A transparent-scan sequence T is obtained from a compact single-detection combinational test set C. It is shown that for the same number of clock cycles required to apply C, the transparent-scan sequence T detects faults more times than C. It is also noted that a transparent-scan sequence based on a combinational test set contains unspecified values. The effects of specifying the unspecified values of the transparent-scan sequence on the quality of the sequence are studied by considering a random specification of these values. A procedure for modifying the scan-select subsequence of a (fully specified) transparent-scan sequence so as to improve its quality as an n-detection test sequence is also described. Finally, the extension of a transparent-scan test sequence into an n-detection test sequence that detects every target fault at least n times is considered. The results show a slower increase in test-application time with n than when combinational test sets are considered

Measurement of Power Consumption in Digital Systems

A study on different measurement configurations for the estimation of power consumption of processing systems is presented. The problem addressed is to measure the energy consumed by a digital system during a number of clock cycles and to assign this consumption to a specific group of instructions. This kind of energy measurement provides the information needed for determining the energy consumption of specific software routines that run on digital processing systems. The proposed configuration is expected to provide clear information about the power behavior of single-chip processing systems as it may monitor the energy consumption during different tasks of operation. Furthermore, it may be integrated in the same chip as a peripheral unit that may be turned on periodically as the front-end circuit of an accurate built-in self-test configuration

Reconfigurable Coprocessor for Multimedia Application Domain

A new reconfigurable architectural template is presented. Such a template is composed of coarse-grained and fine-grained reconfigurable datapath and control to obtain performances at custom designed chip level. To show the adaptability/performance of such architectural template, the architecture has been customized (i.e. datapath and control features of the template have been properly sized) for multimedia application domain. To evaluate complexity and maximum clock frequency of the proposed architecture, it has been synthesized using Synopsys Design Compiler on a standard-cell 0.18 ? m technology. Estimated number of transistors is 335 K, while maximum allowable frequency is 460 MHz. Performances have been evaluated comparing the number of clock cycles and the processing time required to process application domain dominant kernels with commercial devices: we obtained up to 95% reduction with respect to ARM and up to 94% reduction with respect to TMS320C5510 in terms of clock cycles.

Constant-Ratio-Coupled Multi-Grain Digital Synchronizer With Flexible Input-Output Delay Selection for Versatility in Low-Power Applications

The constant-ratio-coupled multi-grain digital synchronizer (CRC-MGsynchronizer) is proposed as a means for making high-speed connections with very low power consumption, both among multiple chips such as processors, controllers, and storage devices, and among on-chip modules. The synchronizer not only provides a wide range of operating frequencies, but is fast locking and only occupies a small area on chip. Therefore, it contributes to large reductions in power consumption and costs. It is suitable for use in various low-power systems (e.g., battery-hungry mobile appliances and low-cost consumer electronic products). Three major techniques were applied to the design: 1)a multi-grain structure for the delay elements, which greatly reduces the number of gates while facilitating locking in a very small number of clock cycles;2) constant-ratio-coupled (CRC) delay lines (measurement versus generation)for flexible selection of the input-output delay; and 3) a new lock stage decision circuit (LSDC) scheme, conferring excellent testability. Moreover,the architecture is all-digital, and thus it has high process portability. By applying these techniques to a DDR memory interface circuit for a mobile application processor fabricated in 130-nm technology, we were able to reduce power consumption by 42% and chip area by 65% compared with a conventional implementation. Furthermore, the novel design spans a frequency range covering 12 times the minimum frequency.

Multiple-Clock-Cycle Architecture for the VLSI Design of a System for Time-Frequency Analysis

Multiple-clock-cycle implementation (MCI) of a flexible system for time-frequency (TF) signal analysis is presented. Some very important and frequently used time-frequency distributions (TFDs) can be realized by using the proposed architecture: (i) the spectrogram (SPEC) and the pseudo-Wigner distribution (WD), as the oldest and the most important tools used in TF signal analysis; (ii) the S-method (SM) with various convolution window widths, as intensively used reduced interference TFD. This architecture is based on the short-time Fourier transformation (STFT) realization in the first clock cycle. It allows the mentioned TFDs to take different numbers of clock cycles and to share functional units within their execution. These abilities represent the major advantages of multicycle design and they help reduce both hardware complexity and cost. The designed hardware is suitable for a wide range of applications, because it allows sharing in simultaneous realizations of the higher-order TFDs. Also, it can be accommodated for the implementation of the SM with signal-dependent convolution window width. In order to verify the results on real devices, proposed architecture has been implemented with a field programmable gate array (FPGA) chips. Also, at the implementation (silicon) level, it has been compared with the single-cycle implementation (SCI) architecture.

PERFORMANCE EVALUATION OF BLAS ON THE TRIDENT PROCESSOR

Different subtasks of an application usually have different computational, memory, and I/O requirements that result in different needs for computer capabilities. Thus, the more appropriate approach for both high performance and simple programming model is designing a processor having multi-level instruction set architecture (ISA). This leads to high performance and minimum executable code size. Since the fundamental data structures for a wide variety of existing applications are scalar, vector, and matrix, our research Trident processor has three-level ISA executed on zero-, one-, and two-dimensional arrays of data. These levels are used to express a great amount of fine-grain data parallelism to a processor instead of the dynamical extraction by a complicated logic or statically with compilers. This reduces the design complexity and provides high-level programming interface to hardware. In this paper, the performance of Trident processor is evaluated on BLAS, which represent the kernel operations of many data parallel applications. We show that Trident processor proportionally reduces the number of clock cycles per floating-point operation by increasing the number of execution datapaths.

Bit Manipulation Accelerator for Communication Systems Digital Signal Processor

This paper proposes application-specific instructions and their bit manipulation unit (BMU), which efficiently support scrambling, convolutional encoding, puncturing, interleaving, and bit stream multiplexing. The proposed DSP employs the BMU supporting parallel shift and XOR (exclusive-OR) operations and bit insertion/extraction operations on multiple data. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18 m standard cell library and the gate count of the BMU is only about 1700 gates. Performance comparisons show that the number of clock cycles can be reduced about for scrambling, convolutional encoding, and interleaving compared with existing DSPs.

Improving test effectiveness of scan-based BIST by scan chain partitioning

Test effectiveness of a test-per-scan built-in self-test (BIST) scheme is highly dependent on the length and number of scan chains. Fewer cycles are used to capture test responses when the length of the scan chains increases and the total number of clock cycles is fixed. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are not observable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments. Multiple capture cycles are inserted to receive test responses during the shift cycles compared to the test-per-scan test scheme. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cycles. Unlike the previous method that drives multiple scan segments by a single scan-in signal, the proposed method uses a new architecture to control all scan segments by different signals. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

A VLSI Architecture for Variable Block Size Video Motion Estimation

With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding, particularly in the area of variable block size video motion estimation (VBSME), are increasing. In this paper, we propose a new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME). The VBS sum of absolute differences (SAD) computation is performed by re-using the results of smaller sub-block computations. These are distributed and combined by incorporating a shuffling mechanism within each processing element. Whereas a conventional 1-D architecture can process only one motion vector (MV), this new architecture can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

Algorithm and architecture for a Galois field multiplicative arithmetic processor

We present a new algorithm for generic multiplicative computations of the form ab/c in GF(p/sup m/), including multiplication, inversion, squaring, and division. The algorithm is based on solving a sequence of congruences that are derived from the theory of Grobner bases in modules over the polynomial ring GF(p)[x]. Its corresponding hardware and software architectures can be successfully used in applications such as error control coding and cryptography. We describe a versatile circuit associated with the algorithm for the most important case p=2. The same hardware can be used for a range of field sizes thus permitting applications in which different levels of error control or of security are required by different classes of user. The operations listed are all performed by the hardware in the same number of clock cycles, which prevents certain side-channel attacks. The loss in performance by having 2m iterations for multiplication is compensated by the full parameterization of the Galois field and the ability to perform division and multiplication in parallel.

Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.

An efficient recursive cell architecture of modified euclid's algorithm for decoding reed-solomon codes

For decoding Reed-Solomon (RS) codes, the Belekamp-Messay algorithm, Euclid's algorithm and modified Euclid's algorithm (MEA) have been developed among which the MEA becomes the most popular decoding scheme. We propose an efficient recursive cell architecture suitable for the MEA. The proposed architecture uses about 25% less clock cycles required in the MEA operation than the conventional scheme. In addition, the number of recursive MEA cells can be reduced when the number of clock cycles spent in the MEA operation is larger than code word length n. Thereby buffer requirement for the received words can be reduced. For demonstration, the MEA circuitry for (128, 124) RS code has been described and the MEA operation is verified through VHDL modeling.

Probabilistic analysis of interconnect coupling noise

Noise simulators and noise avoidance tools are playing an increasingly critical role in the design of deep submicron circuits. However, noise estimates produced by these simulators are often very pessimistic. For large, high-performance industrial ICs, which can contain hundreds of thousands of nets, the worst case estimates of the noise results in thousands of reported violations, without any information about the likelihood of the possible noise violation. In this paper, we present a probabilistic approach to prioritize the violating nets based on the likelihood of occurrence of the reported noise. We derive an upper bound on the probability that the total noise injected on a given victim net by a specific set of aggressors exceeds a threshold. This is equivalent to a lower bound on the expected number of clock cycles required to realize the noise violation for the first time, i.e., mean time-to-failure. If the probability of a failure in a victim is sufficiently small, it is possible that even during the operation of the part for a number of years, the probability of failure on the net is negligible and the net can be assigned a lower priority for the application of noise avoidance strategies. We demonstrate the utility of this approach through experiments carried out on an large industrial processor design using a state-of-the-art industrial noise analysis tool.

Nonscan design for testability for synchronous sequential circuits based on conflict resolution

A testability measure called conflict, based on conflict analysis in the process of sequential circuit test generation is introduced to guide nonscan design for testability. The testability measure indicates the number of potential conflicts to occur or the number of clock cycles required to detect a fault. A new testability structure is proposed to insert control points by switching the extra inputs to primary inputs, using whichever extra inputs of all control points can be controlled by independent signals. The proposed design for testability approach is economical in delay, area, and pin overheads. The nonscan design for testability method based on the conflict measure can reduce many potential backtracks and make many hard-to-detect faults easy-to-detect; therefore, it can enhance actual testability of the circuit greatly. Extensive experimental results are presented to demonstrate the effectiveness of the method.

Low-power digital neuron for SOM implementations

A digital implementation of the self-organising map (SOM) is shown to have reduced power requirements through a strategy of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs requiring two clock cycles, one clock cycle, and half clock cycle per element of the input vector have been constructed and analysed. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%.

Three-dimensional discrete wavelet transform architectures

The three-dimensional (3-D) discrete wavelet transform (DWT) suits compression applications well, allowing for better compression on 3-D data as compared with two-dimensional (2-D) methods. This paper describes two architectures for the 3-D DWT, called the 3DW-I and the 3DW-II. The first architecture (3DW-I) is based on folding, whereas the 3DW-II architecture is block-based. Potential applications for these architectures include high definition television (HDTV) and medical data compression, such as magnetic resonance imaging (MRI). The 3DW-I architecture is an implementation of the 3-D DWT similar to folded 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set performing the calculations for one dimension. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The 3DW-II architecture uses block inputs to reduce the requirement of on-chip memory. It has a central control unit to select which coefficients to pass on to the lowpass and highpass filters. The memory on the chip will be small compared with the input size since it depends solely on the filter sizes. The 3DW-I and 3DW-II architectures are compared according to memory requirements, number of clock cycles, and processing of frames per second. The two architectures described are the first 3-D DWT architectures.