Asynchronous Circuits Research Articles

An Efficient ReRAM-based Accelerator for Asynchronous Iterative Graph Processing

Graph processing has become a central concern for many real-world applications and is well-known for its low compute-to-communication ratios and poor data locality. By integrating computing logic into memory, resistive random access memory (ReRAM) tackles the demand for high memory bandwidth in graph processing. Despite the years’ research efforts, existing ReRAM-based graph processing approaches still face the challenges of redundant computation overhead . It is because the vertices of many subgraphs are ineffectively and repeatedly processed over the ReRAM crossbars for lots of iterations so as to update their states according to the vertices of other subgraphs regardless of the dependencies among the subgraphs. In this paper, we propose ASGraph , a dependency-aware ReRAM-based graph processing accelerator that overcomes the aforementioned performance bottlenecks. Specifically, ASGraph dynamically constructs the subgraph based on the dependencies between vertices’ states and then detects constructed subgraph that owns high value (it is likely that it has accumulated many state propagations from its neighbors and is able to affect more other neighbors) to be preferentially processed. In this way, it makes the vertex states propagate along the dependencies between vertices as much as possible to reduce the redundant computation. Besides, ASGraph employs a hybrid processing scheme to accelerate the state propagations of the tightly connected subgraph, thereby minimizing the redundant computations. Experimental results show that ASGraph achieves 25.5 × and 4.8 × speedup and 70.8 × and 2.2 × energy saving on average compared with the state-of-the-art ReRAM-based graph processing accelerators, i.e., GraphR and GaaS-X, respectively.

Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms

Test Pattern Generators is an important module for testing Asynchronous circuits that guarantee fault detection. In this paper a multi-bit TPGs with tunable LFSR lengths is presented. Our method enables smooth transitions between various word lengths by dynamically selecting LFSR configurations based on control signals. For 4-bit to 7-bit combinational circuits, we have derived a polynomial-based LFSRs and shown effect of stuck-at-fault detections through extensive testing. It includes a discussion of instructional insights regarding fault coverage and digital circuit design. By bridging fixed and flexible BIST solutions, our adaptive TPG design improves fault detection capabilities.

Designing a Multi-Level Caching Forward Index for Recommendation System Services

This paper introduces a forward index based on microservices, which effectively addresses the issue of forward read amplification in recommendation systems through a multi-layer caching mechanism. This allows the forward service to handle a large number of concurrent requests with limited resources while ensuring service stability and final value rate. The paper provides a detailed description of the forward index's data structure design, traffic penetration calculation, and overall service architecture design, dividing the system into three parts: SDK, proxy service, and storage, corresponding to data query, data processing, and data storage respectively. In the SDK design, three components are employed: Cache Slot, synchronous queue, and timer, supporting synchronous, asynchronous, and flexible request forms. The proxy service design handles heterogeneous data and online computation, supporting batch and asynchronous designs, and provides a dynamic data protocol to adapt to the characteristic needs of different microservices. The storage layer design considers performance, cost, and maintainability, utilizing a Cache & SSD model to cope with high-concurrency scenarios.

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

Backpropagation-Based Learning Techniques for Deep Spiking Neural Networks: A Survey.

With the adoption of smart systems, artificial neural networks (ANNs) have become ubiquitous. Conventional ANN implementations have high energy consumption, limiting their use in embedded and mobile applications. Spiking neural networks (SNNs) mimic the dynamics of biological neural networks by distributing information over time through binary spikes. Neuromorphic hardware has emerged to leverage the characteristics of SNNs, such as asynchronous processing and high activation sparsity. Therefore, SNNs have recently gained interest in the machine learning community as a brain-inspired alternative to ANNs for low-power applications. However, the discrete representation of the information makes the training of SNNs by backpropagation-based techniques challenging. In this survey, we review training strategies for deep SNNs targeting deep learning applications such as image processing. We start with methods based on the conversion from an ANN to an SNN and compare these with backpropagation-based techniques. We propose a new taxonomy of spiking backpropagation algorithms into three categories, namely, spatial, spatiotemporal, and single-spike approaches. In addition, we analyze different strategies to improve accuracy, latency, and sparsity, such as regularization methods, training hybridization, and tuning of the parameters specific to the SNN neuron model. We highlight the impact of input encoding, network architecture, and training strategy on the accuracy-latency tradeoff. Finally, in light of the remaining challenges for accurate and efficient SNN solutions, we emphasize the importance of joint hardware-software codevelopment.

Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing.

Navigating normalcy: designing personal health visualizations for pediatric kidney transplant recipients and caregivers.

Patients with chronic illnesses, including kidney disease, consider their sense of normalcy when evaluating their health. Although this concept is a key indicator of their self-determined well-being, they struggle to understand if their experience is typical. To address this challenge, we set out to explore how to design personal health visualizations that aid participants in better understanding their experiences post-transplant, identifying barriers to normalcy, and achieving their desired medical outcomes. Pediatric kidney transplant patients and their caregivers participated in three asynchronous design sessions involving sharing experiences, presenting symbolic objects, and providing feedback on visualizations to understand their perceptions of normalcy post-transplant. Data analysis of design session 1 and 2 comprised deductive and inductive analysis. We used affinity diagramming to identify thematic areas about participants' transplant experiences. Comprehension of design session three normalcy visualizations was also evaluated. Participants effectively engaged in the design sessions, revealing diverse perspectives on their experiences. We found there is a significant need for visualizations that depict normalcy to better inform patients and caregivers about their health. Normalcy Visualizations should incorporate three key design principles: personal values, facilitating peer and self-comparison, and seamlessly communicating abstract concepts to help youth kidney transplant recipients comprehend and contextualize if their transplant experience is normal and what normalcy means to them. By incorporating holistic aspects of patients' and caregivers' lives into personal health visualizations, they can be cognizant of their progress to normalcy and empowered to make decisions that help them feel normal.

A versatile and fast pixel matrix read-out architecture for MAPS

A digital asynchronous logic is proposed as a generic matrix readout for Monolithic active pixel sensors. The architecture is implemented for pixel pitch ranging from 18 to 30µm. Post-layout simulations with realistic hit shapes and rates up to 200MHz/cm2 show that time stamping at the 20ns level can be achieved for a digital power cost below 10mW/cm2.

Design and performance analysis of asynchronous network on chip for streaming data transmission on FPGA

The majority of the system on chip (SoC) uses the network on chip (NoC) as routing ports for data transfer from node-to-node with minimal power consumption and low latency and high throughput. This paper concentrates on the ability to model the asynchronous NoCs on the asynchronous circuits on field programmable gate arrays (FPGAs). A 3×3 NoC and its universal asynchronous receiver transmitter (UART) protocol is designed and its simulation of the Verilog hardware description language (VHDL) code is done and tested on the Artix-7 FPGA kit, the testing processes in done using the Chipscope tool. In order to meet target requirements in terms of power consumption and latency, the label switching (LS) technique is used as routing. The proposed LS-NoC with level-encoded dual-rail (LEDR) encoding technique provides throughput by registering the packet between the different routers and it helps to improve throughput and speed. The effectiveness of the data transfer is measured and analyzed through a synthesis summary in terms of lookup table’s (LUT’s), slice registers, flip flops’s (FF’s), latency, and packet delivery ratio (PDR) for the traffic pattern generator. The proposed NoC is designed for 8×8 and each port size is 21 bits including ID’s of source and destination routers. The results can be justified by following results: improvement of LUTs is about 12%, flip-flops are 7%, improvement of throughput is 23% and delay is reduced by 26%.

Research on the Architectural Design and Performance Optimization of Large Scale Real-Time Chat Systems

With the rapid development of internet technology, large-scale real-time chat systems have become an essential tool for connecting users worldwide. These systems not only support the core functions of social communication but also serve as key platforms for business, education, and remote collaboration. However, the surge in user numbers and the explosive growth in message volume pose unprecedented technical challenges to real-time chat systems, including high concurrency processing, low latency communication, data consistency assurance, and system scalability. This study aims to explore and implement an efficient, stable, and scalable architecture for large-scale real-time chat systems and propose corresponding performance optimization strategies. The research employs literature review, system analysis, prototype design, and performance evaluation methods. It first analyzes the design limitations and performance bottlenecks of existing real-time chat systems. Based on this analysis, a microservices-based system design scheme is proposed, which enhances system performance and reliability through componentized services, message queues, load balancing, and caching mechanisms. In terms of performance optimization, this paper focuses on key technologies such as load balancing algorithms, asynchronous processing mechanisms of message queues, caching strategies, and data storage optimization. Experimental evaluations have confirmed the significant effects of the proposed scheme in handling high-concurrency requests, reducing system latency, and improving data throughput.

Analog Implementation of a Spiking Neuron with Memristive Synapses for Deep Learning Processing

Analog neuromorphic prototyping is essential for designing and testing spiking neuron models that use memristive devices as synapses. These prototypes can have various circuit configurations, implying different response behaviors that custom silicon designs lack. The prototype’s behavior results can be optimized for a specific foundry node, which can be used to produce a customized on-chip parallel deep neural network. Spiking neurons mimic how the biological neurons in the brain communicate through electrical potentials. Doing so enables more powerful and efficient functionality than traditional artificial neural networks that run on von Neumann computers or graphic processing unit-based platforms. Therefore, on-chip parallel deep neural network technology can accelerate deep learning processing, aiming to exploit the brain’s unique features of asynchronous and event-driven processing by leveraging the neuromorphic hardware’s inherent parallelism and analog computation capabilities. This paper presents the design and implementation of a leaky integrate-and-fire (LIF) neuron prototype implemented with commercially available components on a PCB board. The simulations conducted in LTSpice agree well with the electrical test measurements. The results demonstrate that this design can be used to interconnect many boards to build layers of physical spiking neurons, with spike-timing-dependent plasticity as the primary learning algorithm, contributing to the realization of experiments in the early stage of adopting analog neuromorphic computing.

Beyond supervision: An unsupervised spatio-temporal point cloud noise modeling for event vision sensor

Noise modeling is a fundamental unexplored problem in many event camera applications. The noise modeling methods of conventional cameras are inadequate for capturing the intricate noise patterns unique to event cameras. To address this gap, we propose a novel event camera-driven noise modeling approach specifically designed to account for the unique characteristics of event camera data. Given the challenges in generating ground truth data, the proposed method is designed using unsupervised statistical techniques. The proposed noise model is camera-aware, i.e. it allows adaptability to the unique noise patterns of each sensor. It also facilitates asynchronous event processing as applied to downstream computer vision tasks. To validate the proposed noise modeling approach, we conducted extensive experiments in the context of denoising tasks. The results indicate that our noise model accurately represents the noise, leading to state-of-the-art performance across various datasets.

A Forest Fire Smoke Monitoring System Based on a Lightweight Neural Network for Edge Devices

Forest resources are one of the indispensable resources of the earth, which are the basis for the survival and development of human society. With the swift advancements in computer vision and artificial intelligence technology, the utilization of deep learning for smoke detection has achieved remarkable results. However, the existing deep learning models have poor performance in forest scenes and are difficult to deploy because of numerous parameters. Hence, we introduce an optimized forest fire smoke monitoring system for embedded edge devices based on a lightweight deep learning model. The model makes full use of the multi-scale variable attention mechanism of Transformer architecture to strengthen the ability of image feature extraction. Considering the needs of application scenarios, we propose an improved lightweight network model LCNet for feature extraction, which can reduce the parameters and enhance detecting ability. In order to improve running speed, a simple semi-supervised label knowledge distillation scheme is used to enhance the overall detection capability. Finally, we design and implement a forest fire smoke detection system on an embedded device, including the Jetson NX hardware platform, high-definition camera, and detection software system. The lightweight model is transplanted to the embedded edge device to achieve rapid forest fire smoke detection. Also, an asynchronous processing framework is designed to make the system highly available and robust. The improved model reduces three-fourths of the parameters and increases speed by 3.4 times with similar accuracy to the original model. This demonstrates that our system meets the precision demand and detects smoke in time.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

This paper presents a 16-bit, 18-MSPS (million samples per second) flash-assisted successive-approximation-register (SAR) analog-to-digital converter (ADC) utilizing hybrid synchronous and asynchronous (HYSAS) timing control logic based on an on-chip delay-locked loop (DLL). The HYSAS scheme can provide a longer settling time for the capacitive digital-to-analog converter (CDAC) than the synchronous and asynchronous SAR ADC. Therefore, the issue of incomplete settling or ringing in the DAC voltage for cases of either on-chip or off-chip reference voltage can be solved to a large extent. In addition, the foreground calibration of the CDAC’s mismatch is performed with a finite-impulse-response bandpass filter (FIR-BPF) based least-mean-square (LMS) algorithm in an off-chip FPGA (field programmable gate array). Fabricated in 40-nm CMOS process, the prototype ADC achieves 94.02-dB spurious-free dynamic range (SFDR), and 75.98-dB signal-to-noise-and-distortion ratio (SNDR) for a 2.88-MHz input under 18-MSPS sampling rate.

Real-Time Human Pose Estimation Using Machine Learning

Human pose estimation is a pivotal domain within computer vision, underpinning applications from motion capture in cinematic production to sophisticated user interfaces in desktop devices. This research delineates the implementation of real-time human pose estimation within web browsers utilizing TensorFlow.js and the PoseNet model. PoseNet, an advanced machine learning model optimized for browser-based execution, facilitates precise pose detection sans specialized hardware. The primary aim of this study is to integrate PoseNet with TensorFlow.js, achieving efficient real-time pose estimation directly in the browser by leveraging JavaScript, thereby ensuring seamless user interaction and broad accessibility. A modular system architecture is designed, focusing on optimization strategies such as model quantization, asynchronous processing, and on-device computation to enhance performance and privacy preservation. In conclusion, this research establishes a robust framework for deploying PoseNet in web environments, underscoring its potential to revolutionize human-computer interaction within browser-based applications. Our findings contribute significantly to the field of computer vision and machine learning, offering insights into the practical deployment of pose estimation models on widely accessible platforms. Keywords — ReaReal-time Pose Estimation, TensorFlow.js, PoseNet, Machine Learning, Computer Vision, Browser-based Pose Detection, Human-Computer Interaction, Multi-person Tracking, On-device Computation, Asynchronous Processing, Cross-browser Compatibility, Performance Optimization, Privacy-preserving AI, Web-based Machine Learning, Motion Capture, Fitness Tracking, Interactive , Virtual Reality Interfaces, Deep LearningLearning

Neuromorphic Perception and Navigation for Mobile Robots: A Review

With the fast and unstoppable evolution of robotics and artificial intelligence, effective autonomous navigation in real-world scenarios has become one of the most pressing challenges in the literature. However, demanding requirements, such as real-time operation, energy and computational efficiency, robustness, and reliability, make most current solutions unsuitable for real-world challenges. Thus, researchers are fostered to seek innovative approaches, such as bio-inspired solutions. Indeed, animals have the intrinsic ability to efficiently perceive, understand, and navigate their unstructured surroundings. To do so, they exploit self-motion cues, proprioception, and visual flow in a cognitive process to map their environment and locate themselves within it. Computational neuroscientists aim to answer “how” and “why” such cognitive processes occur in the brain, to design novel neuromorphic sensors and methods that imitate biological processing. This survey aims to comprehensively review the application of brain-inspired strategies to autonomous navigation. The paper delves into areas such as neuromorphic perception, asynchronous event processing, energy-efficient and adaptive learning, and the emulation of brain regions vital for navigation, such as the hippocampus and entorhinal cortex.

Monotonic Asynchronous Two-Bit Full Adder

Monotonic circuits are a class of input–output mode (IOM) asynchronous circuits that are relaxed compared to quasi-delay-insensitive (QDI) IOM asynchronous circuits in terms of signaling the completion of internal processing. Some recent works have demonstrated the superiority of monotonic logic over QDI logic for arithmetic circuits such as adders and multipliers. This paper presents a new monotonic asynchronous two-bit full adder (TFA) that can be duplicated and cascaded to form a ripple-carry adder (RCA). While an RCA is a slow adder with respect to synchronous design, with respect to IOM asynchronous design an RCA is a noteworthy adder since it has perhaps the least reverse latency that is not attainable through other IOM asynchronous adders. Conventionally, an RCA is constructed via a cascade of one-bit full adders (OFAs). An OFA adds two input bits along with any carry input and produces a sum bit and any carry output. On the other hand, a TFA simultaneously adds two pairs of input bits along with any carry input and produces two sum bits and any carry output. Using our proposed monotonic TFA, we realized an RCA to compare its performance with RCAs constructed using different asynchronous OFAs, and RCAs constructed using existing TFAs. We considered the popular delay-insensitive dual-rail scheme for encoding the adder inputs and outputs, and two 4-phase handshake protocols, namely return-to-zero handshaking (R0H) and return-to-one handshaking (R1H) for communication separately. We used a 28 nm CMOS process for implementation and considered a 32-bit addition as an example. Based on the design metrics estimated, the following inferences were derived: (i) compared to the RCA using the state-of-the-art monotonic OFA, the RCA incorporating the proposed TFA achieved a 26% reduction in cycle time for R0H and a 28.5% reduction in cycle time for R1H while dissipating almost the same power; the cycle time governs the data application rate in an IOM asynchronous circuit, and (ii) compared to the RCA comprising an early output QDI TFA, the RCA incorporating the proposed TFA achieved a 22.3% reduction in cycle time for R0H and a 25.4% reduction in cycle time for R1H while dissipating moderately less power. Also, compared to the existing early output QDI TFA, the proposed TFA occupies 40.9% less area for R0H and 42% less area for R1H.

Time-triggered scheduling of mixed-critical flows at end-system in asynchronous AFDX avionic network

Avionics Full-DupleX (AFDX) is a switched Ethernet-based network used in modern commercial airplanes for the transmission of command and control avionics flows. These critical flows require deterministic guarantees leading to a lightly loaded network. Aircraft manufacturers envision to carry additional non avionics flows (i.e. video, audio, service) to take advantage of the spare bandwidth. However, it is then compulsory to preserve the real-time guarantees of avionics flows in terms of bounded jitter at the transmitter output and of bounded end-to-end latency. Depending on the type of additional traffic, Quality of Service (QoS) end-to-end guarantees may be offered to the additional flows of lower criticality in terms of reduced delay or bounded jitter for instance. These guarantees can be ensured by scheduling policies at transmitter and switch level. However, an important safety-related constraint is the asynchronous design of avionics distributed systems that prohibits the use of a network-wide synchronization of end systems and switches. Thus, time-triggered networking such as emerging Time-Triggered Ethernet (TTEthernet) or Time-Sensitive Networking (TSN) cannot be leveraged. This paper underlines the benefits of only scheduling flows at the transmitter, which is compatible with the asynchronous safety constraint of avionics systems. We show that it is possible to build a table schedule that carries both critical avionics flows and additional video flows that meet their timing and bandwidth allocation constraints. Therefore, we design scheduling strategies for efficient distribution of flows in the table scheduling whose performance is compared to the optimal schedule minimizing the emission lag of additional flows. Proposed heuristics are constructed such as to favor the network responsiveness for avionics flows thanks to slot over-provisioning. Extensive results on an A350 AFDX industrial configuration show that for a transmitter load of up to 70% of the available bandwidth, the uniform allocation heuristic provides a performance close to optimal in terms of minimum emission lag for additional flows, so offering a practical configuration heuristic to industry.

BRAND: a platform for closed-loop experiments with deep network models.

Objective.Artificial neural networks (ANNs) are state-of-the-art tools for modeling and decoding neural activity, but deploying them in closed-loop experiments with tight timing constraints is challenging due to their limited support in existing real-time frameworks. Researchers need a platform that fully supports high-level languages for running ANNs (e.g. Python and Julia) while maintaining support for languages that are critical for low-latency data acquisition and processing (e.g. C and C++).Approach.To address these needs, we introduce the Backend for Realtime Asynchronous Neural Decoding (BRAND). BRAND comprises Linux processes, termednodes, which communicate with each other in agraphvia streams of data. Its asynchronous design allows for acquisition, control, and analysis to be executed in parallel on streams of data that may operate at different timescales. BRAND uses Redis, an in-memory database, to send data between nodes, which enables fast inter-process communication and supports 54 different programming languages. Thus, developers can easily deploy existing ANN models in BRAND with minimal implementation changes.Main results.In our tests, BRAND achieved <600 microsecond latency between processes when sending large quantities of data (1024 channels of 30 kHz neural data in 1 ms chunks). BRAND runs a brain-computer interface with a recurrent neural network (RNN) decoder with less than 8 ms of latency from neural data input to decoder prediction. In a real-world demonstration of the system, participant T11 in the BrainGate2 clinical trial (ClinicalTrials.gov Identifier: NCT00912041) performed a standard cursor control task, in which 30 kHz signal processing, RNN decoding, task control, and graphics were all executed in BRAND. This system also supports real-time inference with complex latent variable models like Latent Factor Analysis via Dynamical Systems.Significance.By providing a framework that is fast, modular, and language-agnostic, BRAND lowers the barriers to integrating the latest tools in neuroscience and machine learning into closed-loop experiments.

GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs

Recent advances in graph processing on FPGAs promise to alleviate performance bottlenecks with irregular memory access patterns. Such bottlenecks challenge performance for a growing number of important application areas like machine learning and data analytics. While FPGAs denote a promising solution through flexible memory hierarchies and massive parallelism, we argue that current graph processing accelerators either use the off-chip memory bandwidth inefficiently or do not scale well across memory channels. In this work, we propose GraphScale, a scalable graph processing framework for FPGAs. GraphScale combines multi-channel memory with asynchronous graph processing (i.e., for fast convergence on results) and a compressed graph representation (i.e., for efficient usage of memory bandwidth and reduced memory footprint). GraphScale solves common graph problems like breadth-first search, PageRank, and weakly connected components through modular user-defined functions, a novel two-dimensional partitioning scheme, and a high-performance two-level crossbar design. Additionally, we extend GraphScale to scale to modern high-bandwidth memory (HBM) and reduce partitioning overhead of large graphs with binary packing.