NOR Type Research Articles

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

A N ovel NOR Type TCAM Deploy D ual V T cell with OR Type Cascade Match Line Structure

We look over improvements in the schemes of large size content addressable memory (CAM). A CAM is a very important device that executes the routing table function within a single clock cycle in network router to transmit information over the network. CAMs are particularly popular in network switches to classify and sending information packets, they are also helpful in other different applications that require fast information retrieval from routing table. The primary CAM configuration challenge is to decrease power dissipation related with the lot of parallel activity in memory circuitry during search operation. As innovation going on in technology scaling, it continues minimizing the dynamic power dissipation of CAMs, however it also rises the leakage current of transistors. Thus, the static power is turning into a noteworthy bit of the whole power dissipation in CAMs. Here, we introduced a procedure which advantageous for high capacity Ternary Content Addressable Memory (TCAM) that minimize the static power dissipation in SRAM storage cell part and speed up activity in searching part of TCAM cell. We also divide whole memory into equivalent segments which improve performance of our design. We examine the different schemes and introduced the trade-offs of applying the techniques. Simulation and design have done by using Tanned EDA V.16 tool. For recreations of Low power TCAM structures we utilized predictive technology model (PTM) 45nm for high performance (HP) and low power (LP), which incorporate metal gate, high-k and stress effect of CMOS technology.

Heterogeneous Logic: a High Performance and Low Power Non CMOS 4 1 Multiplexer

A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails. Only 16 transistors are required for the actual logic function in the proposed state-of-the-art design. Number of transistors is reduced by distinctly choosing DVL and TGL in the first stage as per the input combination. Later stage of the multiplexer is constructed using SPTL. A required logic style is chosen at first and second stage in accordance with input bit combination to minimize the number of transistors, enhance the speed of logic transition and reduce the average power dissipation. The design and simulation analysis of proposed circuit is carried out at 22nm technology using Pyxis Schematic and Pyxis Simulator. Comparison of wide-ranging simulated results of proposed design, CMOS tree multiplexer and CMOS NOR multiplexer at various supply voltages and frequencies on same technology node manifests that the performance of proposed heterogeneous multiplexer is better in terms of speed and power dissipation. At minimum possible supply voltage of 0.8V and at moderate frequency of 1GHz, the proposed multiplexer achieves, reduced power dissipation of 17.3% and reduced in delay of 9.14%. The count of transistors including inverters is also less compared to CMOS tree type and CMOS NOR type multiplexers. However, robustness of mixed logic style designs is to be improved compared to CMOS designs.

Low Power High Speed Ternary Content Addressable Memory

Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V.

Hardware Implementation of Energy Efficient Deep Learning Neural Network Based on Nanoscale Flash Computing Array

AbstractDeep learning neural network (DNN) can provide efficient approaches to process the increasing unstructured data, such as images, audio, and video. To improve the computing power and the energy efficiency of data processing in DNN, a universal and reconfigurable computing paradigm with the hardware implementation scheme including the convolution, pooling, and fully connected layers is developed based on nanoscale flash computing arrays, which can be massively fabricated. Via precisely tuning the threshold voltage, the fabricated 65 nm nanoscale flash cells can exhibit 16 levels (four bits) of storage states. To confirm the feasibility of the computing paradigm, an exemplary five‐layer DNN is simulated based on the measured data from the nor‐type (NOR) flash memory and exhibits 97.8% recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit database with the speed of 4.2 × 105 fps at 104 MHz operating frequency. The proposed paradigm with low energy and chip cost shows great promise for future energy efficient and massively parallel data processing of DNN.

A Novel Ternary Content Addressable Memory Cell

Ternary content addressable memories (TCAM) are used for parallel searching. The parallel searching, results high speed but consumes more power. For higher search speed applications, NOR type matchline TCAMs are useful. The NOR type matchline TCAM needs high power; therefore, the power reduction is the major objective of many reported designs. Here, a novel TCAM cell is proposed. The proposed Ternary CAM cell power consumption is 32% lesser than the NOR type matchline TCAM cell. Simulations are performed using cadence 45-nm technology.

1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs

In this letter, we propose one-transistor ferroelectric NOR type (Fe-NOR) non-volatile memory based on HfZrOx ferroelectric FETs (FeFETs). The enhanced drain-channel coupling in ultra-short channel FeFETs is utilized to dynamically modulate the memory window of storage cells, thereby resulting in simple erase-, program-, and read-operations. The simulation analysis predicts sub-1V program/erase voltages in the proposed Fe-NOR memory array and, therefore, presents a significantly lower power alternative to conventional FeRAM and NOR flash memories.

A simple wear leveling algorithm for NOR type solid storage device

The role and importance of solid storage devices (SSD) is rapidly increasing for the purpose of data storage. The SSDs are rapidly replacing the old fashioned and traditional magnetic storage medium. Few factors responsible for this metamorphic turnaround are due to the better performance and low power requirement of SSDs. But, as with every pros there are some associated cons. One limiting factor of SSDs in replacing traditional magnetic storage media is its low endurance. These solid state devices can be re-programmed for a limited number of times. Unlike, magnetic storage media, the SSDs can be re-programmed for a limited number of times. Internally, SSDs are organized either in bytes or blocks. Generally, for memory access operations, either the byte or blocks are used. With each write operation, the byte gets worn out and its lifetime decreases. To guard this limiting factor of SSD, wear leveling mechanism is used. Wear leveling mechanism is provided as a feature in flash type SSDs, which evenly distributes the write operation throughout the flash memory and prevents the early wear out of memory. The existing wear leveling mechanism is limited only to flash type SSDs. In this paper, we propose a wear leveling algorithm for SSD and precisely NOR type SSD. NAND types SSDs are well equipped with algorithms to enhance their life and reliability. The algorithm proposed will provide a mechanism that will enhance the life, endurance and reliability of SSD of NOR type.

Fast erase algorithm using flash translation layer in NAND-type flash memory

Flash memory can be classified into NOR type and NAND type. The NOR type memories enables fast reading with byte level I/O is developed into memory for code storage such as ROM BIOS. The NAND type memories cheaper than NOR type and therefore more widely used to larger scale systems. This paper proposed the new file translation system by making a new file structure which can decrease write operations. This file structure reduced write operation frequency of flash memory in file system layer. We can reduced write operation rate because of a write operation rate can be improved the efficiency of file translation operations. Flash Translation Layer (FTL) is to mapping a logical data address to a physical data address in flash memory, its designed to realize erase policy of data in order to perform write operation. The FTL suggests fast erase algorithm reduced write operation through a new file system structure and FTL programming. In addition, we have made the oldest data clean algorithm and then, the most recent data maintained longest as a result of experiment that the recent applied program. In this result, Data tend to be implemented again through the concept of regional and time space which appears automatically when applied program is implemented. This work proves the efficiency of the file system of NAND type flash memories through experiments. Through experiment and realization of the Flash file system, this scheme proved the efficiency of NAND-type flash file system which is required in an embedded system.

Flexible Memristive Memory Array on Plastic Substrates

The demand for flexible electronic systems such as wearable computers, E-paper, and flexible displays has recently increased due to their advantages over present rigid electronic systems. Flexible memory is an essential part of electronic systems for data processing, storage, and communication and thus a key element to realize such flexible electronic systems. Although several emerging memory technologies, including resistive switching memory, have been proposed, the cell-to-cell interference issue has to be overcome for flexible and high performance nonvolatile memory applications. This paper describes the development of NOR type flexible resistive random access memory (RRAM) with a one transistor-one memristor structure (1T-1M). By integration of a high-performance single crystal silicon transistor with a titanium oxide based memristor, random access to memory cells on flexible substrates was achieved without any electrical interference from adjacent cells. The work presented here can provide a new approach to high-performance nonvolatile memory for flexible electronic applications.

相変化チャネルトランジスタを用いた積層型NOR PRAMの検討

相変化チャネルトランジスタを用いた積層型NOR PRAMの検討

Study of stacked NOR type MRAM for universal memory

In this paper stacked NOR type MRAM with vertical spin transistor has been newly proposed. Word line scheme surrounded by vertical spin transistor enable to realize small cell size of 9F2 and fast random access time competitive to DRAM.

CSL-NOR형 SONOS 플래시 메모리의 멀티비트 적용에 관한 연구

NOR type flash 32 <TEX>${\times}$</TEX> 32 way are fabricated by using the typical 0.35 <TEX>${\mu}{\textrm}{m}$</TEX> CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

Scaling of Nanocrystal Memory Cell by Direct Tungsten Bitline on Self-Aligned Landing Plug Polysilicon Contact

This letter reports the first full process integration of nanocrystal memory cell with 4.6 F/sup 2/ area ( NOR type), which is achieved by direct tungsten (W) bitline on self-aligned landing plug polysilicon contact. Prior to the nanocrystals (NCs) formation, surface hydroxylation of the tunnel SiO/sub 2/ by exposure to 1:99 hydrogen flouride (HF) is performed to maintain controllability of NCs. Also, the degradation of the tunnel SiO/sub 2/ caused by HF dipping is overcome to some extent through its fluorination. Robust four-threshold voltage (V/sub th/) states for 2-bit operation per cell are observed due to the localized injected charge and V/sub th/ asymmetry from different reading sensitivity to localized charges.

고집적화된 1TC SONOS 플래시 메모리에 관한 연구

To realize a high integrated flash memory utilizing SONOS memory devices, the NOR type ITC(one Transistor Cell) SONOS flash arrays are fabricated and characterized. This SONOS flash arrays with the common source lines are designed and fabricated by conventional 0.35<TEX>$\mu\textrm{m}$</TEX> CMOS process. The thickness of ONO for memory cells is tunnel oxide of 34<TEX>${\AA}$</TEX>, nitride of 73<TEX>${\AA}$</TEX> and blocking oxide of 34<TEX>${\AA}$</TEX> . To investigate operating characteristics, CHEI(Channel Hot Electron Injection) method and bit line method are selected as the program and 4he erase operation, respectively. The disturbance characteristics ,according to the program/erase/read cycling are also examined. The degradation characteristics are investigated and then the reliability of SONOS flash memory is guaranteed.

Simulation, fabrication and characterization of a 3.3 V flash ZE 2PROM array implemented in a 0.8 μm CMOS process

This paper describes a Zener based flash memory cell (ZE 2PROM), programmed from hot electrons generated by a heavily doped reverse biased p +n + junction attached to the drain. The cell can be implemented in a NOR type memory array. It uses an orthogonal write technique to achieve fast programming with low power dissipation and reduced drain disturbance. The modeling of the charge transfer behavior of the flash ZE 2PROM cell is also done to describe the charging and discharging of the floating gate during programming and erasing. The flash ZE 2PROM arrays were implemented in a 0.8 μm lithography CMOS process flow in which the n-LDD step was replaced with a one sided p + boron implant with a doping level of ∼10 19 cm −3. This minor change to a standard CMOS process, makes the concept highly attractive for embedded memory applications. A programming time of 850 ns at 3.3 V supply was achieved on fabricated test devices.

Subcongenic Analysis of theIdd13Locus in NOD/Lt Mice: Evidence for Several Susceptibility Genes Including a Possible Diabetogenic Role for β2-Microglobulin

AbstractAlthough they share ∼88% of their genome with NOD mice including the H2g7 haplotype, NOR mice remain free of T cell-mediated autoimmune diabetes (IDDM), due to non-MHC genes of C57BLKS/J (BKS) origin. NOR IDDM resistance was previously found to be largely controlled by the Idd13 locus within an ∼24 cM segment on Chromosome 2 encompassing BKS-derived alleles for H3a, B2m, Il1, and Pcna. NOD stocks carrying subcongenic intervals of NOR Chromosome 2 were utilized to more finely map and determine possible functions of Idd13. NOR- derived H3a-Il1 (∼6.0 cM) and Il1-Pcna (∼1.2 cM) intervals both contribute components of IDDM resistance. Hence, the Idd13 locus is more complex than originally thought, since it consists of at least two genes. B2m variants within the H3a-Il1 interval may represent one of these. Monoclonal Ab binding demonstrated that dimerizing with the β2ma (NOD type) vs β2mb isoform (NOR type) alters the structural conformation, but not total expression levels of H2g7 class I molecules (e.g. Kd, Db). β2m-induced alterations in H2g7 class I conformation may partially explain findings from bone marrow chimera analyses that Idd13 modulates IDDM development at the level of non-hematopoietically derived cell types controlling selection of diabetogenic T cells and/or pancreatic β cells targeted by these effectors. Since trans-interactions between relatively common and functionally normal allelic variants may contribute to IDDM in NOD mice, the search for Idd genes in humans should not be limited to functionally defective variants.

A 98 mm/sup 2/ die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm/sup 2/ die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-/spl mu/m CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 /spl mu/s/Byte programming speed.

Performance of the 3-D PENCIL flash EPROM cell and memory array

A promising new 3-D Programmable Erasable Nonvolatile CylIndricaL (PENCIL) flash EPROM cell that offers significant area and performance advantages over conventional planar approaches has been implemented in a novel memory array. The 3-D PENCIL cell is a vertical device formed on the sidewalls of an etched silicon pillar. The cell is a single transistor stacked gate structure with the floating gate and control gate completely surrounding the pillar. Current flows vertically from the bit line contact at the top of the pillar to the source lying at the bottom of the pillar. When implemented in a novel self-aligned array, the cell size approaches the square of the minimum pitch and has an area less than half that of the conventional NOR type structure. The cell and array architecture also promise to be highly scalable. Experimental data reveals that the cells have up to 3/spl times/ larger read current than comparable planar cells, are suitable for 5 V only operation and have fast program and erase speeds at moderate voltage levels. Uniformity and endurance characteristics are also promising.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >