Simulation, fabrication and characterization of a 3.3 V flash ZE 2PROM array implemented in a 0.8 μm CMOS process

Abstract

This paper describes a Zener based flash memory cell (ZE 2PROM), programmed from hot electrons generated by a heavily doped reverse biased p +n + junction attached to the drain. The cell can be implemented in a NOR type memory array. It uses an orthogonal write technique to achieve fast programming with low power dissipation and reduced drain disturbance. The modeling of the charge transfer behavior of the flash ZE 2PROM cell is also done to describe the charging and discharging of the floating gate during programming and erasing. The flash ZE 2PROM arrays were implemented in a 0.8 μm lithography CMOS process flow in which the n-LDD step was replaced with a one sided p + boron implant with a doping level of ∼10 19 cm −3. This minor change to a standard CMOS process, makes the concept highly attractive for embedded memory applications. A programming time of 850 ns at 3.3 V supply was achieved on fabricated test devices.