NOR Operations Research Articles

Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency

Traditional von Neumann computing architectures suffer from high energy and lower speed as compared to the requirements of modern applications like those required in neural network accelerators. A modified differential eight transistor (8 + T) static random access memory (SRAM)-based in-memory computing (IMC) structure was presented for realizing bit-wise Boolean logic operations. The 8 + T SRAM-IMC is designed at the 32 nm technology node with throughput of 2.1849, 2.4815, 2.5795, 2.6240, 2.6495, 2.6619, 2.6690, 2.6732, and 2.6749 giga outputs per second for 0.5 to 1.3 V supply voltage range, respectively. The differential 8T cell used to implement logic operations supports NAND and NOR operations with minimal overhead while also performing the standard storage operation with added stability over the conventional 6T and 8T SRAM cells. The SRAM-IMC offers reliable Boolean logic operations by using asymmetric sensing strategy for all process corners, TT, SS, SF, FS, and FF for an operating temperature range of 220 K to 400 K. Monte Carlo simulation considering global threshold voltage deviation of 50 mV was performed for various operating conditions to study the impact of variations on design parameters such as latency.

Dual-Mode Reconfigurable Split-Gate Logic Transistor through Van der Waals Integration.

As silicon-based transistors approach their physical size limitations, two-dimensional material-based reconfigurable functional electronic devices are considered the most promising novel device architectures beyond Moore strategies. While these devices have garnered significant attention, they often require complex device fabrication processes and extra electric fields. Additionally, the device performance is usually limited by the metal-semiconductor interface properties. In this Letter, we have constructed a reconfigurable logic device based on a WSe2 transistor with a nanofloating gate and split-gates through van der Waals integration. This device achieves a small Schottky barrier height due to the van der Waals contacts. By varying the split-gate biases, we can realize volatile reconfigurable homojunctions as well as AND, OR, NOR, and NAND logic operations with just a single device. Furthermore, with the charge trapping effect of nanofloating gate, we can also achieve nonvolatile reconfigurable homojunctions, as well as AND and OR logic operations. The volatile and nonvolatile logic operations are similar to the short-term plasticity and long-term plasticity, respectively, of synapses in the human brain. This work offers a potential approach for creating novel reconfigurable functional electronic devices with a simple fabrication process and low cost.

High-fidelity decryption technology for visual cryptography based on incoherent optical polarization XNOR operation

In this paper, we propose an optical high-fidelity decryption technology for Visual Cryptography (VC) based on incoherent optical polarization exclusive NOR (XNOR) operation. The plaintext image is divided into two binary ciphertexts by the Random-Grid-based Visual Secret Sharing (RGVSS) algorithm. These ciphertexts are printed onto the polarizing films with orthogonal polarization. The P- and S-polarizing pixels in the polarizing films represent the “black” and “white” pixels of the ciphertexts, respectively. Due to the optical transmission property of polarizing film, the pixel in the decrypted image appears bright only when the stacked pixels for the two ciphertexts have the same polarizing orientation. High-fidelity image decryption is then achieved. The proposed technology has been successfully demonstrated through simulation and experimentation. Thanks to its advantages of no pixel expansion, incoherent illumination, being free of computer assistance, and flexibility of ciphertext carriers, this method provides a broad prospect for convenient, large-format, high-fidelity information recovery applications for VC.

All-optical neuromorphic XOR and XNOR operation utilizing a photonic spiking neuron based on a passive add-drop microring resonator.

We propose a concise hardware architecture supporting efficient exclusive OR (XOR) and exclusive NOR (XNOR) operations, by employing a single photonic spiking neuron based on a passive add-drop microring resonator (ADMRR). The threshold mechanism and inhibitory dynamics of the ADMRR-based spiking neuron are numerically discussed on the basis of the coupled mode theory. It is shown that a precise XOR operation in the ADMRR-based spiking neuron can be implemented by adjusting temporal differences within the inhibitory window. Additionally, within the same framework, the XNOR function can also be carried out by accumulating the input power over time to trigger an excitatory behavior. This work presents a novel, to the best of our knowledge, and pragmatic technique for optical neuromorphic computing and information processing utilizing passive devices.

All-Optical XOR, AND, OR, NOT, NOR, NAND, and XNOR Logic Operations Based on M-Shaped Silicon Waveguides at 1.55 μm.

Silicon waveguides are essential to integrated photonics, which is where optical and electronic components are coupled together on a single silicon chip. These waveguides allow for the integration of signal processing and optical transmission, which advances data centers, telecommunications, and other optical applications. Thus, our study involves the simulation of essential all-optical logic operations, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, and utilizes M-shaped silicon optical waveguides at a wavelength of 1.55 μm. This simulation is conducted through Lumerical FDTD solutions. The suggested waveguide comprises four identical slots, configured in the shape of the letter 'M', and all of which are formed of core silicon and silica cladding. These logic operations work based on constructive and destructive interferences that are caused by phase changes in the input optical beams. The contrast ratio (CR) is employed to quantitatively and comparatively assess the degree to which the target logic operations are efficiently executed. The simulation results indicate that, compared to other reported designs, the considered logic functions constructed using the proposed waveguide can be implemented with higher CRs. The outcomes of this paper can be utilized regarding the implementation of optoelectronic combinational logic circuits of enhanced functionality.

Harnessing Multistability: A Novel Approach to Optical Logic Gate Construction Using Erbium-Doped Fiber Lasers

We present an innovative method harnessing multistability within a diode-pumped erbium-doped fiber laser to construct logic gates. Our approach involves manipulating the intensity of external noise to regulate the probability of transitioning among four concurrent attractors. In this manner, we facilitate the realization of OR, AND, NOR, and NAND logic operations, aligning with the coexisting period-1, period-3, period-4, and period-5 orbits. Employing detrended fluctuation analysis, we establish equilibrium in the probability distributions of these states. The obtained results denote a substantial advancement in the field of optical logic gate development, representing a pivotal stride toward the seamless integration of an all-optical logic gate within laser oscillator-based systems.

The Amplified DNA Logic Gates Based on Aptamer-Receptor Recognition for Cell Detection and Bioimaging.

A powerful and accurate method for identifying and isolating cells would be of great importance due to its sensitivity, gentleness and effectiveness. Here, we designed a receptor-based DNA logic device that allows Boolean logic analysis of multiple cells. For ease of expression, the molecules on the cell surface that can bind to the aptamer are referred to as "receptors". This DNA logic device sends signals based on cell surface sgc8c and sgc4f receptor expression by performing NOT, NOR, AND and OR logic operations, and amplifies and evaluates the signals using HCR. Meanwhile, the release of ICG from the endopore of HMSNs is controlled by affecting structural changes in the DNA logic device. This approach can accurately identify and treat multiple cells on demand based on the presence or absence of cell-specific receptors, facilitating the development of personalized medicine.

Polymerase Chain Reaction-based Biomolecular Logic Gate for NAND and NOR Operations

Polymerase Chain Reaction-based Biomolecular Logic Gate for NAND and NOR Operations

MAGIC-DHT: Fast in-memory computing for Discrete Hadamard Transform

Discrete Hadamard transform (DHT) is a signal processing tool that decomposes an arbitrary input vector into a superposition of Walsh functions. Due to its wide range of applications in processing big data, a fast and energy-efficient hardware design for DHT with high throughput capability is essential. Processing in memory (PIM) allows the in-place computation to reduce the data traffic, which is a major speed bottleneck in the existing computing. In this work, we propose an efficient hybrid parallel PIM-based computation for DHT. Our proposed method explores the recursive computation of DHT and is based on the memristor-aided logic (MAGIC) gates in which the arithmetic operations are carried out via simple logic NOR operation. We propose two in-memory computing methods for the DHT encoding process. At the arithmetic level, to improve efficiency, we propose to share the intermediate results between addition and subtraction in DHT in the first method called MAGIC-DHT-1D which provides an average speedup of 1.12× over the recently proposed DigitalPIM for 1D DHT. Furthermore,MAGIC-DHT-1D also outperforms SIMPLER in terms of energy and energy density in average. We also propose a second method, called MAGIC-DHT-2D, to share the carrier independent computation cycles among multi-bit parallel addition and subtraction. At the algorithm level, we also explore both row and column-based PIM NOR computing in the same crossbar to avoid the transposition operation required in the 2D DHT process. MAGIC-DHT-2D provides an average speedup of 4.84× and 7.25× over two state-of-the-art methods DigitalPIM and SIMPLER, respectively for each complete set of 2D DHT computing cycles. Our numerical results further show that our proposed optimized methods can lead up to 56.19× and 6.90× speed-up, as well as 57.84× and 5.96× higher throughput over NVIDIA RTX Titan GPU to compute 1D DHT and 2D DHT, respectively.

Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

Design of an all-optical multi-logic operation-integrated metamaterial-based terahertz logic gate.

Terahertz logic gates play a vital role in optical signal processing and terahertz digitization. Herein, a strategy to design an all-optical terahertz logic gate device composed of metamaterials with a semiconductor-metal hybrid is proposed; accordingly, a concrete logic gate composed of Ge embedded-in Au stripe supported by a Si board is presented theoretically. Simulation results reveal the dependence of the terahertz transmission spectra on the different illuminations in the device. Based on the illumination-transmission response, the designed device can realize the NOR or OR Boolean operation. The effects of the width of the Ge-Au stripe as well as the Si board on the transmission spectra and logic performance were also investigated.

Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks

A novel synaptic architecture based on a NAND flash memory structure is proposed as a high-density synapse capable of exclusive NOR (XNOR) operation for binary neural networks (BNNs). For the first time, a 4T2S-based synaptic architecture with a complementary input voltage that implements an equivalent bitwise XNOR operation is proposed. Two adjacent NAND flash strings connected with the word lines are used as one synaptic string with four input transistors connected to the bit-line. By changing the threshold voltage of the NAND flash cells and input voltages in a complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (∼7 × 105) of the NAND flash cells and differential sensing scheme can implement high-density and highly reliable binary neural networks without error correcting codes (ECC), which can reduce the burden of the complementary metal–oxide–semiconductor (CMOS) overhead. Despite the string structure of NAND flash memory, the parallel read scheme significantly reduces the read-out latency when compared to the sequential read scheme. In addition, we show that with only 1 erase/program pulse, sufficiently low bit-error rate (7.6 × 10−9 %) is achieved without the conventional incremental step pulse programming (ISPP) scheme. Finally, the estimated synapse density of V-NAND flash memory with 128 stacks is ∼103 times that of the 2T2R synapse in resistive random access memory (RRAM).

Sensitive Logic Nanodevices with Strong Response for Weak Inputs

AbstractSensitive sensing is critical when developing new calculation systems with weak input signals (ISs). In this work, a “weak‐inputs‐strong‐outputs” strategy was proposed to guide the construction of sensitive logic nanodevices by coupling an input‐induced reversible DNA computing platform with a hybridization chain reaction‐based signal amplifier. By rational design of the sequence of computing elements (CEs) so as to avoid cross‐talking between ISs and signal amplifier, the newly formed logic nanodevices have good sensitivity to the weak ISs even at low concentrations of CEs, and are able to perform YES, OR, NAND, NOR, INHIBIT, INHIBIT‐OR and number classifier operation, showing that the DNA calculation proceeds in dilute solution medium that greatly improves the calculation proficiency of logic nanodevices without the confinement of the lithography process in nanotechnology.

Sensitive Logic Nanodevices with Strong Response for Weak Inputs

Sensitive sensing is critical when developing new calculation systems with weak input signals (ISs). In this work, a "weak-inputs-strong-outputs" strategy was proposed to guide the construction of sensitive logic nanodevices by coupling an input-induced reversible DNA computing platform with a hybridization chain reaction-based signal amplifier. By rational design of the sequence of computing elements (CEs) so as to avoid cross-talking between ISs and signal amplifier, the newly formed logic nanodevices have good sensitivity to the weak ISs even at low concentrations of CEs, and are able to perform YES, OR, NAND, NOR, INHIBIT, INHIBIT-OR and number classifier operation, showing that the DNA calculation proceeds in dilute solution medium that greatly improves the calculation proficiency of logic nanodevices without the confinement of the lithography process in nanotechnology.

An Analytical Approach for Implementing an All-Optical NOR Operation Using Amplitude Squeezed Light

An Analytical Approach for Implementing an All-Optical NOR Operation Using Amplitude Squeezed Light

Applicable Image Security Based on New Hyperchaotic System

Hyperchaotic systems are widely applied in the cryptography domain on account of their more complex dynamical behavior. In view of this, the greatest contribution of this paper is that a two-dimensional Sine coupling Logistic modulated Sine (2D-SCLMS) system is proposed based on Logistic map and Sine map. By a series of analyses, including Lyapunov index (LE), 0–1 test, two complexity analysis methods, and two entropy analysis methods, it is concluded that the new 2D-SCLMS map is hyperchaotic with a wider range of chaos and more complex randomness. The new system combined with two-dimensional Logistic-Sine Coupling Mapping (2D-LSCM) is further applied to an image encryption application. SHA-384 is used to generate the initial values and parameters of the two chaotic systems. Symmetric keys are generated during this operation, which can be applied to the proposed image encryption and decryption algorithms. The encryption process and the decryption process of the new image encryption approaches mainly include pixel scrambling, exclusive NOR (Xnor), and diffusion operations. Multiple experiments illustrate that this scheme has higher security and lower time complexity.

Single‐Component CMOS‐Like Logic using Diketopyrrolopyrrole‐Based Ambipolar Organic Electrochemical Transistors

AbstractComplementary circuits based on organic electrochemical transistors (OECTs) are attractive for the development of inexpensive and disposable point‐of‐care bioelectronic devices. Ambipolar OECTs, which employ a single channel material, could decrease the fabrication complexity and manufacturing costs of such circuits. An ideal channel material for ambipolar OECTs should be electrochemically stable in aqueous environments, afford facile ion insertion for both cations and anions, and also facilitate high and balanced electron and hole transport. In this study, triethylene glycol functionalized diketopyrrolopyrrole (DPP)‐based polymer is proposed for the development of ambipolar OECTs. It is shown that DPP‐based OECTs have a high and comparable figure of merit for both n‐ and p‐type operations. Logic NOT, NAND, and NOR operations with corresponding complementary circuits constructed from identical DPP‐based OECT devices are demonstrated. This study is an important step toward the development of sophisticated complementary metal–oxide–semiconductor‐like logic circuits using single‐component OECTs.

Logic and in-memory computing achieved in a single ferroelectric semiconductor transistor

Exploring materials with multiple properties who can endow a simple device with integrated functionalities has attracted enormous attention in the microelectronic field. One reason is the imperious demand for processors with continuously higher performance and totally new architecture. Combining ferroelectric with semiconducting properties is a promising solution. Here, we show that logic, in-memory computing, and optoelectrical logic and non-volatile computing functionalities can be integrated into a single transistor with ferroelectric semiconducting α-In2Se3 as the channel. Two-input AND, OR, and non-volatile NOR and NAND logic operations with current on/off ratios reaching up to five orders, good endurance (1000 operation cycles), and fast operating speed (10 μs) are realized. In addition, optoelectrical OR logic and non-volatile implication (IMP) operations, as well as ternary-input optoelectrical logic and in-memory computing functions are achieved by introducing light as an additional input signal. Our work highlights the potential of integrating complex logic functions and new-type computing into a simple device based on emerging ferroelectric semiconductors.

DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs

The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit.
 Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed

Numerical simulation of all-optical logic gates based on hybrid-cavity semiconductor lasers.

All-optical switch and multiple logic gates have been demonstrated using a hybrid-cavity semiconductor laser composed of a square microcavity and a Fabry-Perot cavity experimentally. In this paper, two-section tri-mode rate equations with optical injection terms are proposed and applied to study all-optical logic gates of NOT, NOR, and NAND operations utilizing the hybrid-cavity laser. Steady-state and dynamical characteristics of all-optical multiple logic gates are simulated, taking into account the influence of mode frequency detuning, gain suppression coefficients, mode Q factor, injection energy, and biasing current. All-optical logic NOT, NOR, and NAND gates up to 20, 15, and 20 Gbit/s are obtained numerically with dynamic extinction ratios of over 20, 20, and 10 dB, respectively, which are potential response speeds of the all-optical logic gates based on the hybrid-cavity semiconductor lasers.