NOR Operations Research Articles

Photonic crystal based on mott phase change material as all-optical bandgap switch and composite logic gate

We propose a composite photonic crystal based on phase change material to realize the photonic bandgap dependent all-optical switch in the mid-near infrared band. The demonstrated photonic crystal all-optical switch is built on the surface of integrated silicon waveguide on standard SOI and matched with standard CMOS lithography process. The communication light in the silicon waveguide is modulated by VO2 with Mott metal-insulator transition at near room temperature which results in the shifting of optical bandgap. The simulations based on the finite difference time domain method show that the photonic crystal device possess a modulation depth of 0.95 and an insertion loss of 1.27 dB for fundamental TM mode propagating at 1550 nm. We also discuss the influence of device length and thickness of photonic crystal on the switching performance. Moreover, the compound logic gate derived from proposed switch is also designed to provide NOT and NOR operations simultaneously for the next-generation all-optical chips. Due to the reversible phase transition process of VO2 photonic crystal, the proposed device can realize the fast state switching of light and is expected to provide some help for the research of silicon-based optical chips.

MTL: Memristor Ternary Logic Design

The nanoscale implementations of ternary logic circuits are particularly attractive because of high information density and operation speed that can be achieved by using emerging memristor technologies. Memristor is a nanoscale device with nonvolatility and adjustable multilevel states, which creates an intriguing opportunity for the implementation of ternary logic operations. This paper proposes a novel memristor-based design for stateful ternary logic, including AND, OR, NOT, NAND, NOR, and COPY operations. In the proposed memristor ternary logic (MTL) design, the resistance of memristor is the only logic state variable for representing the input and output. By sensing the value of the input memristors, the resistance of the output memristor changes accordingly. Furthermore, the MTL gates are not only capable of performing logic operations, but also storing logic values. To illustrate the potential of the methodology, a single-input-three-output ternary decoder is designed by using the proposed ternary logic circuits. Simulation results verify the effectiveness of the presented design.

Terahertz Spoof Surface Plasmonic Logic Gates.

SummaryLogic gates are important components in integrated photonic circuitry. Here, a series of logic gates to achieve fundamental logic operations based on linear interference in spoof surface plasmon polariton waveguides are demonstrated at terahertz frequencies. A metasurface-based plasmonic source is adopted to couple free-space terahertz radiation into surface waves, followed by a funnel-shaped metasurface to efficiently couple the surface waves to the waveguides built on a domino structure. A single Mach-Zehnder waveguide interferometer can work as logic gates for four logic functions: AND, NOT, OR, and XOR. By cascading two such interferometers, NAND and NOR operations can also be achieved. Experimental investigations are supported by numerical simulations, and good agreement is obtained. The logic gates have compact sizes and high intensity contrasts for the output “1” and “0” states. More complicated functions can be envisioned and will be of great value for future terahertz integrated computing.

Memristor‐based stateful logic gates for multi‐functional logic circuit

Memristor-based stateful logic circuits can perform logic operations and logic value storage, which creates an intriguing opportunity for the implementation of an advanced computational architecture. This study proposes a novel memristor-based stateful logic implementation. Specifically, the presented approach is capable of realising two-input or multi-input AND, OR, NAND and NOR operations, and single-input COPY and NOT operations. In each logic gate, non-volatile resistances of memristor are used as input and output states, thus enabling stateful logic operations. Compared with several existing approaches, the proposed method can lead to a multi-functional stateful logic circuit, performing multiple stateful logic operations simultaneously. The effectiveness of the proposed design is demonstrated with the simulation results of MATLAB and SPICE.

Performance analysis of multilogic all-optical structure based on nonlinear signal processing in SOA

All-optical signal processing in optical technology is the most reliable process that mitigates the limitations of speed and processing power in electronics by replacing the electronic components with the equivalent optical switching components. All-optical switches are very important in communication and computing, as most communication around the globe is carried on optical fibers. Optical switching is effectively performed in high data rate systems through all-optical gates. The nonlinear signal processing in semiconductor optical amplifier (SOA) is the key element for implementing various optical gate logics. In this paper, combination of optical gates such as all-optical AND, OR, NOT, XOR, NOR and XNOR operations are successfully simulated in single structure. The performance analysis of each gate and its cascaded feature is analyzed by varying the structural and functional parameters of SOA’s active region. The simulation results confirm that the proposed design can be implemented at high data rate of more than 10Gbps with good quality factor and extinction ratio of around 12 dB.

Scalable radiative thermal logic gates based on nanoparticle networks

We discuss the design of the thermal analog of logic gates in systems made of a collection of nanoparticles. We demonstrate the possibility to perform NOT, OR, NOR, AND and NAND logical operations at submicrometric scale by controlling the near-field radiative heat exchanges between their components. We also address the important point of the role played by the inherent non-additivity of radiative heat transfer in the combination of logic gates. These results pave the way to the development of compact thermal circuits for information processing and thermal management.

Digital Biologically Plausible Implementation of Binarized Neural Networks With Differential Hafnium Oxide Resistive Memory Arrays.

The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the brain to achieve this energy efficiency: the absence of separation between computing and memory functions and reliance on low-precision computation. The emergence of resistive memory technologies indeed provides an opportunity to tightly co-integrate logic and memory in hardware. In parallel, the recently proposed concept of a Binarized Neural Network, where multiplications are replaced by exclusive NOR (XNOR) logic gates, offers a way to implement artificial intelligence using very low precision computation. In this work, we therefore propose a strategy for implementing low-energy Binarized Neural Networks that employs brain-inspired concepts while retaining the energy benefits of digital electronics. We design, fabricate, and test a memory array, including periphery and sensing circuits, that is optimized for this in-memory computing scheme. Our circuit employs hafnium oxide resistive memory integrated in the back end of line of a 130-nm CMOS process, in a two-transistor, two-resistor cell, which allows the exclusive NOR operations of the neural network to be performed directly within the sense amplifiers. We show, based on extensive electrical measurements, that our design allows a reduction in the number of bit errors on the synaptic weights without the use of formal error-correcting codes. We design a whole system using this memory array. We show on standard machine learning tasks (MNIST, CIFAR-10, ImageNet, and an ECG task) that the system has inherent resilience to bit errors. We evidence that its energy consumption is attractive compared to more standard approaches and that it can use memory devices in regimes where they exhibit particularly low programming energy and high endurance. We conclude the work by discussing how it associates biologically plausible ideas with more traditional digital electronics concepts.

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

In-memory processing can dramatically improve the latency and energy consumption of computing systems by minimizing the data transfer between the memory and the processor. Efficient execution of processing operations within the memory is therefore, a highly motivated objective in modern computer architecture. This article presents a novel automatic framework for efficient implementation of arbitrary combinational logic functions within a memristive memory. Using tools from logic design, graph theory and compiler register allocation technology, we developed synthesis and in-memory mapping of logic execution in a single row (SIMPLER), a tool that optimizes the execution of in-memory logic operations in terms of throughput and area. Given a logical function, SIMPLER automatically generates a sequence of atomic memristor-aided logic (MAGIC) NOR operations and efficiently locates them within a single size-limited memory row, reusing cells to save area when needed. This approach fully exploits the parallelism offered by the MAGIC NOR gates. It allows multiple instances of the logic function to be performed concurrently, each compressed into a single row of the memory. This virtue makes SIMPLER an attractive candidate for designing in-memory single instruction, multiple data (SIMD) operations. Compared to the previous work (that optimizes latency rather than throughput for a single function), SIMPLER achieves an average throughput improvement of $435\times $ . When the previous tools are parallelized similarly to SIMPLER, SIMPLER achieves higher throughput of at least $5\times $ , with $23\times $ improvement in area and $20\times $ improvement in area efficiency. These improvements more than fully compensate for the increase (up to 17% on average) in latency.

A 0.94 μW 611 KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS

Conventional computers based on the Von Neumann architecture conduct computation with repeated data movements between their separate processing and memory units, where each movement takes time and energy. Unlike this approach, we experimentally study memory that can perform computation as well as store data within a generic memory array in a non-Von Neumann architecture way. Memory array can innately perform NOR operation that is functionally complete and thus realize any Boolean functions like inversion (NOT), disjunction (OR) and conjunction (AND) operations. With theoretical exploration of memory array performing Boolean computation along with storing data, we demonstrate another potential of memory array with a test chip fabricated in a 90 nm logic process. Measurement results confirm valid in-situ memory logic operations in a 32-kbit memory system that successfully operates down to 135 mV consuming 130 nW at 750 Hz, reducing power and data traffic between the units by five orders of magnitude at the sacrifice of performance.

Reconfigurable spin logic device using electrochemical potentials

A reconfigurable spin logic device is realized using an asymmetric quantum well displaying strong Rashba spin splitting. This design is developed to remove the inefficient spin injection process and to utilize the Rashba-effect-induced electrochemical potential shifts. In this logic device, two ferromagnetic electrodes were deposited on two quantum well channels, respectively. The magnetization orientations of the ferromagnetic electrodes determine the function of the logic operation, and the polarity of the charge current is assigned to the logic input. The output voltage corresponds to the difference between potentials of the two ferromagnetic terminals, which read the electrochemical potentials of the individual quantum well channels. The detected signal induced by the Rashba channel is observed to be two orders of magnitude greater than the spin injection signal from the ferromagnetic source into the semiconductor channel. Four logic functions, i.e., the AND, OR, NAND, and NOR operations, are illustrated for a single device up to room temperature.

Reconfigurable Field-Effect Transistor as a Synaptic Device for XNOR Binary Neural Network

A reconfigurable field-effect transistor (RFET) with memory functionality is proposed as a new high-density synaptic device capable of exclusive NOR (XNOR) operation for a binary neural network (BNN). A RFET with three gates is used in this letter, consisting of two program gates (PGs) electrically connected to each other and a control gate (CG) between the PGs. By changing the polarity of the PG bias or the polarity of the charge trapped in Si3N4 layer on the PGs, the RFET operates as an ${n}$ - or a ${p}$ -MOSFET having a CG as a switching gate. The XNOR operation is successfully demonstrated in a fabricated RFET. The on/off current ratio (the ratio of 1 to 0 in the result of the XNOR operation) is ~104 and the current is ~1 nA/ $\mu \text{m}$ . Using a RFET as a synaptic device for a BNN is efficient in terms of the area (~8F2/synapse) because XNOR operation can be performed using only one RFET.

Flexible memristor‐based LUC and its network integration for Boolean logic implementation

Memristor is a nanoscale electronic element with variable resistance that depends on the amount and direction of the charge passing through it. As a promising candidate, this memristive element opens up a new approach for the implementation of Boolean logic operations. In this study, a flexible logic unit circuit (LUC) based on a practical memristor model is proposed, which is able to perform the AND, OR, NOT, NOR, and NAND gate operations by different switch settings. Unlike existing memristor-based logic implementation, the initialisation is not necessary for the proposed method, and the total delay can be effectively reduced, especially for time-sequence inputs. Furthermore, the concept of the memristor-based logic network is developed by multiple memristor-based LUCs connected in series and parallel. The circuit simulation demonstrates that the presented logic network is capable of realising multi-input-multi-output logic operations with compact structure, high efficiency, and sufficient accuracy.

Bilobal architecture is a requirement for calmodulin signaling to CaV1.3 channels

Calmodulin (CaM) regulation of voltage-gated calcium (CaV) channels is a powerful Ca2+ feedback mechanism that adjusts Ca2+ influx, affording rich mechanistic insights into Ca2+ decoding. CaM possesses a dual-lobed architecture, a salient feature of the myriad Ca2+-sensing proteins, where two homologous lobes that recognize similar targets hint at redundant signaling mechanisms. Here, by tethering CaM lobes, we demonstrate that bilobal architecture is obligatory for signaling to CaV channels. With one lobe bound, CaV carboxy tail rearranges itself, resulting in a preinhibited configuration precluded from Ca2+ feedback. Reconstitution of two lobes, even as separate molecules, relieves preinhibition and restores Ca2+ feedback. CaV channels thus detect the coincident binding of two Ca2+-free lobes to promote channel opening, a molecular implementation of a logical NOR operation that processes spatiotemporal Ca2+ signals bifurcated by CaM lobes. Overall, a unified scheme of CaV channel regulation by CaM now emerges, and our findings highlight the versatility of CaM to perform exquisite Ca2+ computations.

Simulation and demonstration of electro-optic digital logic gates based on a single microring resonator

We propose and demonstrate directed optical digital logic function which can perform several logic gates using a single microring resonator. The mode operations achieved are logic buffer, inverter, AND, NAND, OR and NOR operations. Numerical simulations, in order to analyze its static as well as dynamic responses, are carried out. In addition, we also present the fundamental numerical principles used by the simulation software in order to fully justify the simulation results. These principles are divided into three components, structure based free carrier distribution principles, change in refractive index of the waveguide and the scattering analysis on the microring resonator coupling region.

High‐performance engineered gate transistor‐based compact digital circuits

A novel method for designing and realising compact digital circuits by engineering MOSFET gate electrode is proposed. The novelty is the use of gate engineered single devices in the pull-up (PU) and pull-down (PD) paths of a static CMOS gate instead of multiple transistors as used in conventional CMOS implementations of circuits. Herein, two input NAND, NOR, and exclusive-OR (XOR) gates employing the proposed gate engineering concept are designed and simulated. Engineered gate N-type MOS and P-type MOS are used for PD and pull-up circuits, respectively. Since only two devices are used for a complete circuit: one in PU network and other in PD network; therefore, area and power of the proposed circuits get reduced significantly in comparison with the conventional static CMOS circuits. Mixed mode simulations have shown that the proposed technique realises NAND, NOR and XOR operations perfectly and it can be extended to realise other combinational and sequential circuits easily.

Water soluble cationic porphyrin showing pH-dependent optical responses to G-quadruplexes: Applications in pH-sensing and DNA logic gate

A water soluble cationic porphyrin derivative 5,10,15,20-tetra-{4-[3-(1-methyl-1-piperidinyl) propoxy]phenyl}porphyrin (TMPipPrOPP), which showed attractive pH-dependent optical responses to G-quadruplexes, was synthesized and characterized. Under molecular crowding conditions, a stable TMPipPrOPP/G-quadruplex complex was formed in acidic pH range. Alkalization of the system to neutral and basic pH caused destruction of the complex due to reduced electrostatic interactions. The formation and destruction of the TMPipPrOPP/G-quadruplex complex was reversibly adjusted by pH, accompanied by repeated on-off switching of the colorimetric and fluorescent responses of TMPipPrOPP to G-quadruplexes. In comparison, no optical responses were observed for single-stranded, duplex and i-motif DNAs in the tested pH range (5.0–8.5). Besides highlighting the importance of designing novel drugs targeting G-quadruplexes in specific genome regions, this work may also provide a useful tool for G-quadruplex-based biosensing and nanomachine construction. One example is the design of colorimetric and fluorescent sensors for ratiometric pH-sensing. The proposed sensing platform can be used not only for highly sensitive pH-sensing in a narrow biological pH range, but also for pH detection in a broad range. Another example is the construction of DNA-based dual-output all-optical molecular logic gates that can perform basic AND, NAND, OR, NOR, INHIBIT and IMPLICATION logic operations.

Resistor-transistor logic circuits using vertical-type organic transistors

ABSTRACTNOR gate operation using organic devices was demonstrated based on resistor-transistor logic (RTL). The RTL was composed of an OR gate using two single layered devices as input resistors and a NOT gate (inverter) using a vertical-type metal base organic transistor (MBOT). The input resistors were connected to the base electrode of the MBOT. When either input was turned from low to high voltage, the output voltage changed from high to low, indicating NOR operation. Dynamic characteristics of the RTL circuit was also evaluated, and operation frequency was estimated to be 300 Hz.

Formation of holographic polymer-dispersed liquid crystal memory by angle-multiplexing recording for optically reconfigurable gate arrays.

Formation of holographic polymer-dispersed liquid crystal (HPDLC) memory for an optically reconfigurable gate array is discussed for angle-multiplexing recording by controlling the laser interference exposure in LC composites. The successive laser illumination system to record the various configuration contexts at the specified region and angle in HPDLC memory is constructed by using the combination of a half-mirror and a photomask placed on the motorized stages under the control of a personal computer. The effect of laser exposure energy on the formation of holographic memory is investigated by measuring diffraction intensity as a function of exposure energy during the grating formation process and observing the internal grating structure by scanning electron microscopy. The optical reconfiguration in the gate-array VLSI is executed for configuration contexts of OR and NOR operations shown as logical operators that are reconstructed by laser irradiation at different incident angles for a specified region in the HPDLC memory.

Metal‐Ion‐Triggered Exonuclease III Activity for the Construction of DNA Colorimetric Logic Gates

The logic system is obtained by using a series of double-stranded (ds) DNA templates with mismatched base pairs (T-T or C-C) and ion-modulated exonuclease III (Exo III) activity, in which the Exo III cofactors, Hg(2+) and Ag(+) ions, are used as inputs for the activation of the respective scission of Exo III based on the formation of T-Hg(2+) -T or C-Ag(+) -C base pairs. Additionally, two kinds of signal probes are utilized to transduce the logic operations. One is the two split G-rich DNA strands that are used to design the OR, AND, INHIBIT, and XOR gates, whereas the other is the self-assembled split G-quadruplex structure to construct NOR, NAND, IMPLICATION, and XNOR operations based on DNA hybridization and strand displacement. In the presence of hemin, the split G-quadruplex biocatalyzes the formation of a colored product, which is an output signal for the different logic gates. Thus, we have constructed a complete set of colorimetric DNA logic gates based on the Exo III and split G-quadruplex for the first time. In addition, we are able to effortlessly recognize the logic output signals by the naked eye and their simplicity and cost-effective design is the most apparent feature for the logic gates developed in this work.

Designs of all-optical NOR gates using SOA based MZI

The paper investigates the non-linear behavior of semiconductor optical amplifier with Mach–Zehnder interferometer (SOA-MZI) configuration which makes it to work as a logic gate. The two designs of NOR gate based on SOA-MZI have been verified. The basic principal of both designs are same. The summation of data pulses have been taken and inverted to perform a NOR operation. In the design, the first 3dB coupler creates a phase difference of π/2 in clock pulse and data pulse while passing through two interferometer arms. The clock and data pulses pass through SOA which attenuates the clock pulse wherever the data pulse is present. After passing through second 3dB coupler a phase difference of π/2 is again created. Therefore, if the clock pulse is in the same phase will be added and if it is out of phase, will be canceled. The designs have been investigated at different bit-rates to achieve higher extinction ratio (ER), Q-factor and bit-error rate (BER) for different pump currents of SOA.