Non-volatile Technologies Research Articles

Voltage-Controlled Bimeron-Torques Switching of In-Plane Magnetization.

Controlling the out-of-plane magnetization in nanodevices via electric currents has played a pivotal role in advancing high-impact data storage and nonvolatile logic technologies within spintronic devices. However, the in-plane magnetization materials, which are more accessible than their out-of-plane counterparts, are less favored in terms of switching efficiency and magnetization stability. This is due to their larger switching barriers, resulting in a higher critical switching current in the commonly used spin-transfer torques or spin-orbit torques magnetic random-access memory. Here, we propose the use of voltage-controlled bimeron-torques to switch in-plane magnetization for ultralow energy consumption magnetic random-access memory. In this mechanism, magnetic bimerons act as spin-angular-momentum carriers as well as momentum transfer media rather than that of electrical spin currents in spin-transfer torques or spin-orbit torques. We address the microscopic origin of this mechanism and demonstrate its validity with two examples: Co(MoTe_{2})_{2} and HgInP_{2}O_{6} monolayers, respectively. The mechanism overcomes the restriction of perpendicular magnetization and avoids Joule heating, thereby providing additional pathways for electrical manipulation of magnetic materials.

Field-free spin-orbit torque switching assisted by in-plane unconventional spin torque in ultrathin [Pt/Co

Electrical manipulation of magnetization without an external magnetic field is critical for the development of advanced non-volatile magnetic-memory technology that can achieve high memory density and low energy consumption. Several recent studies have revealed efficient out-of-plane spin-orbit torques (SOTs) in a variety of materials for field-free type-z SOT switching. Here, we report on the corresponding type-x configuration, showing significant in-plane unconventional spin polarizations from sputtered ultrathin [Pt/Co]N, which are either highly textured on single crystalline MgO substrates or randomly textured on SiO2 coated Si substrates. The unconventional spin currents generated in the low-dimensional Co films result from the strong orbital magnetic moment, which has been observed by X-ray magnetic circular dichroism (XMCD) measurement. The x-polarized spin torque efficiency reaches up to −0.083 and favors complete field-free switching of CoFeB magnetized along the in-plane charge current direction. Micromagnetic simulations additionally demonstrate its lower switching current than type-y switching, especially in narrow current pulses. Our work provides additional pathways for electrical manipulation of spintronic devices in the pursuit of high-speed, high-density, and low-energy non-volatile memory.

Van der Waals ferroelectrics: Progress and an outlook for future research directions

The recent discovery of van der Waals (vdW) ferroelectric materials has inspired their incorporation into numerous nonvolatile technologies and shown potential promise for various device applications. Here in this perspective, we evaluate the recent developments in the field of vdW ferroelectric devices, with discussions focusing on vdW heterostructure ferroelectric field-effect transistors and vdW ferroelectric memristor technologies. Additionally, we discuss some of the many open questions that persist in these technologies and possible pathways research can take to answer these questions and further advance the understanding of vdW ferroelectric materials.

The Third Dimension of Ferroelectric Domain Walls.

Ferroelectric domain walls are quasi-2D systems that show great promise for the development of nonvolatile memory, memristor technology, and electronic components with ultrasmall feature size. Electric fields, for example, can change the domain wall orientation relative to the spontaneous polarization and switch between resistive and conductive states, controlling the electrical current. Being embedded in a 3Dmaterial, however, the domain walls are not perfectly flat and can form networks, which leads to complex physical structures. In this work, the importance of the nanoscale structure for the emergent transport properties is demonstrated, studying electronic conduction in the 3D network of neutral and charged domain walls in ErMnO3 . By combining tomographic microscopy techniques and finite element modeling, the contribution of domain walls within the bulk is clarified and the significance of curvature effects for the local conduction is shown down to the nanoscale. The findings provide insights into the propagation of electrical currents in domain wall networks, reveal additional degrees of freedom for their control, and provide quantitative guidelines for the design of domain-wall-based technology.

Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems

Deep neural networks generate and process large volumes of data, posing challenges for low-resource embedded systems. In-memory computing has been demonstrated as an efficient computing infrastructure and shows promise for embedded AI applications. Among newly-researched memory technologies, racetrack memory is a non-volatile technology that allows high data density fabrication, making it a good fit for in-memory computing. However, integrating in-memory arithmetic circuits with memory cells affects both the memory density and power efficiency. It remains challenging to build efficient in-memory arithmetic circuits on racetrack memory within area and energy constraints. To this end, we present an efficient in-memory convolutional neural network (CNN) accelerator optimized for use with racetrack memory. We design a series of fundamental arithmetic circuits as in-memory computing cells suited for multiply-and-accumulate operations. Moreover, we explore the design space of racetrack memory based systems and CNN model architectures, employing co-design to improve the efficiency and performance of performing CNN inference in racetrack memory while maintaining model accuracy. Our designed circuits and model-system co-optimization strategies achieve a small memory bank area with significant improvements in energy and performance for racetrack memory based embedded systems.

Photoactive electrically switchable van der Waals semiconductor NbOI2

Room temperature van der Waals ferroelectric materials whose ferroelectricity may survive down to atomic layer limit are highly desirable for device miniaturization. In this article, we present the optically active reconfigurable room temperature rectification in a recently predicted ferroelectric van der Waals material NbOI2. NbOI2 devices with a thin (∼17-unit cells) single crystalline channel and inert graphite electrodes were assembled into two-terminal devices which showed >100 × photoresponse to 405 nm laser. By DC poling on a 1-μm-channel NbOI2 device, the photocurrent changed from symmetric to single-Schottky-diode type. The polarity of such rectification can be switched back and forth by DC poling along opposite directions. Such reconfigurability evidences the existence of in-plane room temperature ferroelectricity in thin NbOI2 and its potential in nonvolatile optoneuromorphic computing and nonvolatile technologies.

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments.

Energy-Efficient Instruction Delivery in Embedded Systems with Domain Wall Memory

As performance and energy-efficiency improvements from technology scaling are slowing down, new technologies are being researched in hopes of disrupting results. Domain wall memory (DWM) is an emerging non-volatile technology that promises extreme data density, fast access times and low power consumption. However, DWM access time depends on the memory location distance from access ports, requiring expensive shifting. This causes overheads on performance and energy consumption. In this article, we implement our previously proposed shift-reducing instruction memory placement (SHRIMP) on a RISC-V core in RTL, provide the first thorough evaluation of the control logic required for DWM and SHRIMP and evaluate the effects on system energy and energy-efficiency. SHRIMP reduces the number of shifts by 36% on average compared to a linear placement in CHStone and Coremark benchmark suites when evaluated on the RISC-V processor system. The reduced shift amount leads to an average reduction of 14% in cycle counts compared to the linear placement. When compared to an SRAM-based system, although increasing memory usage by 26%, DWM with SHRIMP allows a 73% reduction in memory energy and 42% relative energy delay product. We estimate overall energy reductions of 14%, 15% and 19% in three example embedded systems.

Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies

In this era of nanoscale technologies, the inherent characteristics of some nonvolatile devices, such as resistive random access memory (ReRAM), phase-change material (PCM), and spintronics, can emulate stochastic functionalities. Traditionally, these devices have been engineered to suppress the stochastic switching behavior as it poses reliability concerns for memory storage and logic applications. However, leveraging stochasticity in such devices led to a renewed interest in hardware-software codesign of stochastic algorithms since the CMOS-based implementations of stochastic algorithms involve cumbersome circuitry to generate “stochastic bits.” In this article, we consider two classes of problems: deep neural networks (DNNs) and combinatorial optimization. The rapidly growing demands of artificial intelligence (AI) have sparked an interest in energy-efficient implementations of large DNNs, with binary representations of synaptic weights and neuronal activities. Stochasticity plays an important role in leveraging the benefits of these binary representations, leading to model compression and optimization during training. In combinatorial optimization, such as graph coloring or traveling salesman problems, stochastic algorithms, such as the Ising computing model, have been shown to be effective. These problems require exhaustive computational procedures, and the Ising model uses a natural annealing agent to achieve near-optimal solutions in a reasonable timescale, without getting stuck in “local minima.” In this article, we present a broad review of stochastic computing utilizing the stochastic switching characteristics of devices based on nanoscale nonvolatile technologies. We show how to codesign of the devices and algorithms that can enable optimal solutions for both combinatorial problems and binary neural networks for local learning and inference. Directly mapping the nonvolatile device characteristics to the stochastic algorithms without the need for storing the bits in a separate memory leads to efficient use of hardware.

Spin–orbit torques in structures with asymmetric dusting layers

Current-induced spin–orbit torques (SOTs) in heavy metal/ferromagnet heterostructures have emerged as an efficient method for magnetization switching with applications in nonvolatile magnetic memory and logic devices. However, experimental realization of SOT switching of perpendicular magnetization requires an additional inversion symmetry breaking, calling for modifications of the conventional SOT heterostructures. In this work, we study SOTs and deterministic switching of perpendicular magnetization by inserting different asymmetric dusting layers at the heavy metal/ferromagnet interface. Similar to the previous works with lateral structural asymmetry, we study the emergence of current-induced perpendicular effective magnetic fields (Hzeff). By examining three different material combinations of heavy metal/dusting layers (W/IrMn, Pt/IrMn, and W/Ta), we shed light on the origins of Hzeff; we show that Hzeff is generically created in all the studied asymmetric structures, has a close correlation with the interfacial magnetic anisotropy, and is independent of the signs of spin Hall angles of the materials. Furthermore, we show that the induction of Hzeff enables field-free deterministic SOT switching of perpendicular magnetization. Our results can be used in designing SOT heterostructures for practical applications in nonvolatile technologies.

Simulation study of memristor aided logic (MAGIC) based on CMOS NOR gate

Memristor is a non-volatile new technology memory where the data stored as a resistance which the performance is influenced by the stateful logic design. Therefore, this study is an attempt to investigate the performance of the MAGIC NOR Gate stateful logic design using LTSPICE and targeted to 2 bits memory application. The objective is to investigate the performance of memristor based stateful logic logic design and schematics for memory application. Furthermore, the study been carried out by implementing the MAGIC NOR gate stateful logic schematic, then simulate the design in order to see the effects of performance including the electrical parameters compared to the others. Evidently, the improvement of MAGIC NOR gate contributes in reducing the number of NOR gate and CMOS count. Besides, the MAGIC NOR gates takes parallel inputs topology and eliminate the threshold voltage compared to IMPLY logic. Nevertheless, larger numbers of memristor required to stable the output consistency in MAGIC NOR gate schematic.

Unconventional Charge-Spin Conversion in Weyl-Semimetal WTe2.

An outstanding feature of topological quantum materials is their novel spin topology in the electronic band structures with an expected large charge-to-spin conversion efficiency. Here, a charge-current-induced spin polarization in the type-II Weyl semimetal candidate WTe2 and efficient spin injection and detection in a graphene channel up to room temperature are reported. Contrary to the conventional spin Hall and Rashba-Edelstein effects, the measurements indicate an unconventional charge-to-spin conversion in WTe2 , which is primarily forbidden by the crystal symmetry of the system. Such a large spin polarization can be possible in WTe2 due to a reduced crystal symmetry combined with its large spin Berry curvature, spin-orbit interaction with a novel spin-texture of the Fermi states. A robust and practical method is demonstrated for electrical creation and detection of such a spin polarization using both charge-to-spin conversion and its inverse phenomenon and utilized it for efficient spin injection and detection in the graphene channel up to room temperature. These findings open opportunities for utilizing topological Weyl materials as nonmagnetic spin sources in all-electrical van der Waals spintronic circuits and for low-power and high-performance nonvolatile spintronic technologies.

Phase Change Materials for Nonvolatile, Solid‐State Reflective Displays: From New Structural Design Rules to Enhanced Color‐Changing Performance

AbstractWith the arrival of omnimedia era, there has been an increasing demand for energy‐saving, colorful, and portable displays. Traditional display technologies, such as electrophoresis and electronic ink display suffer from low color switching speed and poor color richness. Due to their high performances, phase change materials (PCMs)‐based nonvolatile, solid‐state reflective display coatings have become the most promising materials for new portable display technology. Existing researches mainly focus on improving the color‐changing performance of coatings by optimizing film structural parameters, but ignore improving the performance by designing new PCMs. Here, this study reveals the color‐changing mechanisms of display coatings through a combination of experiments, first‐principles calculations, spectral fitting, and optical simulation. It is found that reducing the vacancy concentrations of PCMs can increase the color‐changing performance of coatings owing to the increase in p–p coupling strength. Based on previous reports and the new insights into p–p coupling strength, this study proposes three structural design principles of ideal PCMs (low ionicity, a limited degree of hybridization, and high p–p coupling strength) and predicts new PCM candidates for display applications. This study opens a broad avenue for developing nonvolatile display technologies and material selection.

Functional Read Enabling In-Memory Computations in 1Transistor—1Resistor Memory Arrays

`In-memory computing' is an emerging paradigm that attempts to embed some aspects of logic computations inside memory arrays leading to higher throughput and lesser energy-consumption. Consequently, various in-memory compute proposals using emerging non-volatile technologies based on functional read- wherein multiple word-lines are simultaneously activated and a Boolean function of the constituent activated rows is read, is being extensively investigated. In this brief, we first show that the conventional sensing scheme for such functional reads, operated on 1 Transistor - 1 Resistor (1T-1R) memory arrays, is limited theoretically by low sense-margin. We demonstrate that the sense-margin does not improve even if the ON-OFF resistance difference is increased from low values to considerably higher values. Subsequently, we present a new sensing scheme based on skewed sense-amplifiers and staggered world-line activation as a method for enabling functional read operations. We show that in-memory XOR, IMP (implication) and bit-wise comparison can be easily implemented through the proposed scheme.

8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing

Large-scale digital computing almost exclusively relies on the von Neumann architecture, which comprises separate units for storage and computations. The energy-expensive transfer of data from the memory units to the computing cores results in the well-known von Neumann bottleneck. Various approaches aimed toward bypassing the von Neumann bottleneck are being extensively explored in the literature. These include in-memory computing based on CMOS and beyond CMOS technologies, wherein by making modifications to the memory array, vector computations can be carried out as close to the memory units as possible. Interestingly, in-memory techniques based on CMOS technology are of special importance due to the ubiquitous presence of field-effect transistors and the resultant ease of large-scale manufacturing and commercialization. On the other hand, perhaps the most important computation required for applications such as machine learning, etc., comprises the dot-product operation. Emerging nonvolatile memristive technologies have been shown to be very efficient in computing analog dot products in an in situ fashion. The memristive analog computation of the dot product results in much faster operation as opposed to digital vector in-memory bitwise Boolean computations. However, challenges with respect to large-scale manufacturing coupled with the limited endurance of memristors have hindered rapid commercialization of memristive-based computing solutions. In this paper, we show that the standard 8 transistor (8T) digital SRAM array can be configured as an analoglike in-memory multibit dot-product engine (DPE). By applying appropriate analog voltages to the read ports of the 8T SRAM array and sensing the output current, an approximate analog–digital DPE can be implemented. We present two different configurations for enabling multibit dot-product computations in the 8T SRAM cell array, without modifying the standard bit-cell structure. We also demonstrate the robustness of the present proposal in presence of nonidealities such as the effect of line resistances and transistor threshold voltage variations. Since our proposal preserves the standard 8T-SRAM array structure, it can be used as a storage element with standard read–write instructions and also as an on-demand analoglike dot-product accelerator.

Dynamics of magnetoelectric reversal of an antiferromagnetic domain

When electric and magnetic fields are applied together on a magnetoelectric antiferromagnet, the domain state is subject to reversal. Although the initial and final conditions are saturated single-domain states, the process of reversal may decompose into local multi-domain switching events. In thin films of Cr2O3, the magnetoelectric coercivity and the switching speed found from experiments are considerably lower than expected from magnetic anisotropy, similar to Brown's paradox in ferromagnetic materials. Multi-domain effects originate because antiferromagnetic domain walls are metastably pinned by lattice defects, not due to reduction of magnetostatic energy, which is negligible. This paper theoretically analyzes domain reversal in thin-film magnetoelectric antiferromagnets in the form of nucleation, domain wall propagation, and coherent rotation. The timescales of reversal mechanisms are modeled as a function of applied magnetoelectric pressure. The theory is assessed with reference to latest experimental works on magnetoelectric switching of thin-film Cr2O3: domain wall propagation is found to be dominant and responsible for switching in the experiments. The results bear implications in the energy-delay performance of ME memory devices utilizing antiferromagnetic insulators, which are prospective for nonvolatile technology.

Origin of negative resistance in anion migration controlled resistive memory

Resistive random access memory (RRAM) is one of the most promising emerging nonvolatile technologies for the futuristic memory devices. Resistive switching behavior often shows negative resistance (NR), either voltage controlled or current controlled. In this work, the origin of a current compliance dependent voltage controlled NR effect during the resetting of anion migration based RRAM devices is discussed. The N-type voltage controlled NR is a high field driven phenomena. The current conduction within the range of a certain negative voltage is mostly dominated by space charge limited current. But with the higher negative voltage, a field induced tunneling effect is generated in the NR region. The voltage controlled NR is strongly dependent on the compliance current. The area independent behavior indicates the filamentary switching. The peak to valley ratio (PVR) is > 5. The variation of PVR as a function of the conduction band offset is achieved. Compared to other reported works, based on the PVR, it is possible to distinguish the RRAM types. Generally, due to the higher electric field effect on the metallic bridge during RESET, the electrochemical metallization type RRAM shows much higher PVR than the valance change type RRAM.

Switching a Perpendicular Ferromagnetic Layer by Competing Spin Currents.

An ultimate goal of spintronics is to control magnetism via electrical means. One promising way is to utilize a current-induced spin-orbit torque (SOT) originating from the strong spin-orbit coupling in heavy metals and their interfaces to switch a single perpendicularly magnetized ferromagnetic layer at room temperature. However, experimental realization of SOT switching to date requires an additional in-plane magnetic field, or other more complex measures, thus severely limiting its prospects. Here we present a novel structure consisting of two heavy metals that delivers competing spin currents of opposite spin indices. Instead of just canceling the pure spin current and the associated SOTs as one expects and corroborated by the widely accepted SOTs, such devices manifest the ability to switch the perpendicular CoFeB magnetization solely with an in-plane current without any magnetic field. Magnetic domain imaging reveals selective asymmetrical domain wall motion under a current. Our discovery not only paves the way for the application of SOT in nonvolatile technologies, but also poses questions on the underlying mechanism of the commonly believed SOT-induced switching phenomenon.

NV-Heaps

Persistent, user-defined objects present an attractive abstraction for working with non-volatile program state. However, the slow speed of persistent storage (i.e., disk) has restricted their design and limited their performance. Fast, byte-addressable, non-volatile technologies, such as phase change memory, will remove this constraint and allow programmers to build high-performance, persistent data structures in non-volatile storage that is almost as fast as DRAM. Creating these data structures requires a system that is lightweight enough to expose the performance of the underlying memories but also ensures safety in the presence of application and system failures by avoiding familiar bugs such as dangling pointers, multiple free()s, and locking errors. In addition, the system must prevent new types of hard-to-find pointer safety bugs that only arise with persistent objects. These bugs are especially dangerous since any corruption they cause will be permanent.

A PEALD Tunnel Dielectric for Three-Dimensional Non-Volatile Charge-Trapping Technology

In this paper we compare a novel plasma-enhanced atomic layer deposition (PEALD) oxide with more conventional HTO and ISSG oxides. We show that, remarkably for a deposited oxide, the oxide quality is, both in terms of field-to-breakdown and SILC generation, comparable to that of ISSG thermal oxide. Finally, we show that data retention of SONOS stack with PEALD is significantly better than for stacks with ISSG tunnel oxide. PEALD oxide is, therefore, a promising choice for 3D non-volatile flash technologies.