Floating Gate Nonvolatile Memory Research Articles

Effects of blocking oxide layer types on the performance of nonvolatile floating gate memory containing AgInSbTe-SiO2 nanocomposite thin films

Influence of blocking oxide layer types on the performance of nonvolatile floating gate memory (NFGM) containing AgInSbTe (AIST)-SiO2 nanocomposite as the charge-trapping layer was investigated. In the NFGM containing a 7-nm thick SiO2 blocking oxide layer deposited by plasma-enhanced chemical vapor deposition (PECVD), a fairly large memory window (ΔVFB) shift of 20.9V with the charge density of 1.3×1013cm−2 at ±15V gate voltage sweep was achieved. As to the NFGM containing HfO2 blocking oxide layer, the device performance was inferior to that of PECVD-SiO2 device due to the diffusion of HfO2 into the nanocomposite layer. Interdiffusion resulted in the formation of HfSiOx phase and oxygen defects which might act as the leakage paths, consequently deteriorating the charge trapping efficiency of AIST nanocrystals (NCs) embedded in nanocomposite layer. Analytical results illustrated that the film quality and barrier height feature of blocking oxide layer are essential to form the deep trap sites in the programming layer to achieve a satisfactory NFGM performance with long-term reliability.

Investigation of charge trapping mechanism for nanocrystal-based organic nonvolatile floating gate memory devices by band structure analysis

This paper investigates the charge trapping mechanism and electrical performance of CdSe nanocrystals, such as nanoparticles and nanowires in organic floating gate memory devices. Despite of same chemical component, each nanocrystals show different electrical performances with distinct trapping mechanism. CdSe nanoparticles trap holes in the memory device; on the contrary, nanowires trap electrons. This phenomenon is mainly due to the difference of energy band structures between nanoparticles and nanowires, measured by the ultraviolet photoelectron spectroscopy. Also, we investigated the memory performance with C-V characteristics, charging and discharging phenomena, and retention time. The nanoparticle based hole trapping memory device has large memory window while the nanowire based electron trapping memory shows a narrow memory window. In spite of narrow memory window, the nanowire based memory device shows better retention performance of about 55% of the charge even after 104 sec of charging. The contrasting performance of nanoparticle and nanowire is attributed to the difference in their energy band and the morphology of thin layer in the device.

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated, in which polysilicon is sandwiched between oxide layers as a floating gate. Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed. The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing (P/E) operations at various P/E voltages are discussed. The simulated results show that present memory exhibits a large memory window of 57.5 V, and a high read current on/off ratio of ≈ 103. Compared with the reported experimental results, these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects, which shows great promise in device designing and practical application.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices.

Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells

This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiOx-cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in ID–VG characteristics is presented after the ‘Write’ cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II–VI layer as the gate insulator.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

This paper describes the use of II–VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeOx-cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II–VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrodinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Memory Devices Based on the Nanoparticle Silicon Floating Gate Double-Barrier Structure

Thin film transistors with nanoparticles silicon floating-gate are fabricated by plasma enhanced chemical vapor deposition. It should be noted that SiO2acts as both a tunneling and a blocking layer. Meanwhile, some np-Si dots are embedded within SiO2layers. The electrical characteristic of the devices are measured by semiconductor parameter analyzer at room temperature. These Thin film transistors show a good device performance with a high charge-carrier mobility of 33 cm2/vs and a large on/off ratio of 1.2×106. Moreover, the capability of written and erasing was demonstrated. This indicates that thin film transistors can be operated as rewritable nonvolatile floating gate memory devices.

Nonvolatile floating gate memory characteristics of Sb2Te–SiO2 nanocomposite thin films

Nonvolatile floating gate memory (NFGM) device composed of Sb2Te nanocrystals (NCs) as the charge-storage traps embedded in SiO2 matrix was prepared by the target-attachment sputtering method at various nitrogen (N2) incorporation conditions. Via post annealing at 450°C in ambient air, the sample prepared at the condition N2/Ar=0.1 exhibited a maximum memory window (ΔVFB) shift=4.4V and charge density=4.2×1012cm−2 under ±7V gate voltage sweep. N2 incorporation not only reduced the Sb2Te NC size to about 5nm, but also suppressed the oxygen defects and antimony oxides in the sample. Feasibility of the Sb2Te chalcogenide NCs to NFGM fabrication with the simplified process and relatively low annealing temperature is demonstrated.

Nonvolatile floating gate memory containing AgInSbTe–SiO2 nanocomposite layer and capping the HfO2/SiO2 composite blocking oxide layer

An extremely large memory window shift of about 30.7 V and high charge storage density = 2.3 × 1013 cm−2 at ±23 V gate voltage sweep were achieved in the nonvolatile floating gate memory (NFGM) device containing the AgInSbTe (AIST)–SiO2 nanocomposite as the charge trap layer and HfO2/SiO2 as the blocking oxide layer. Due to the deep trap sites formed by high-density AIST nanocrystals (NCs) in the nanocomposite matrix and the high-barrier-height feature of the composite blocking oxide layer, a good retention property of the device with a charge loss of about 16.1% at ±15 V gate voltage stress for 104 s at the test temperature of 85 °C was observed. In addition to inhibiting the Hf diffusion into the programming layer, incorporation of the SiO2 layer prepared by plasma-enhanced chemical vapor deposition in the sample provided a good Coulomb blockade effect and allowed significant charge storage in AIST NCs. Analytical results demonstrated the feasibility of an AIST-SiO2 nanocomposite layer in memory device fabrication with a simplified processing method and post-annealing at a comparatively low temperature of 400 °C in comparison with previous NC-based NFGM studies.

Formation of CoSi2/CoSixNy Nanocrystals for Nonvolatile Memory Application

Nonvolatile nanocrystal memories recently have been one of the promising candidates to replace traditional floating gate nonvolatile memory because the discrete nanocrystal as the charge storage media have effectively improved data retention under endurance test for the device scaling down. In this study, CoSi2 nanocrystal surrounded with CoSixNy shell structure was proposed by rapid thermal annealing a nitrogen incorporated CoSi layer, which was deposited by sputtering CoSi target in the mixture gas of Ar+N2 or Ar+NH3, to improve data retention. The structures and elements composition of nanocrystal were analyzed by transmission electron microscopy (TEM) and X-ray photoelectron spectroscopy (XPS), and the electrical characteristics of nanocrystals memories were defined by C-V curves. Because of the extra CoSixNy shell, the proposed memory can exhibit good data retention to 10 years.

Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

Nonvolatile Silicon Memory Using GeO x -Cladded Ge Quantum Dots Self-Assembled on SiO2 and Lattice-Matched II–VI Tunnel Insulator

This paper presents fabrication and characterization of a quantum dot-based floating gate nonvolatile memory device with site-specific self-assembly of germanium oxide-cladded germanium (GeOx-Ge) quantum dots on SiO2 and ZnS/ZnMgS/ZnS (II–VI lattice-matched high-κ dielectric) tunnel insulator material. These monodispersed and individually cladded quantum dots have the potential to store charge uniformly in the floating gate and are well suited for nonvolatile memory applications.

Effect of Nitrogen Incorporation to $\hbox{AgInSbTe-SiO}_{2}$ Nanocomposite Thin Films Applied to Nonvolatile Floating Gate Memory

Nonvolatile floating gate memory devices containing AgInSbTe-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocomposites as the charge trapping layers prepared by target attached sputtering method at various nitrogen incorporation conditions were investigated. The nitrogen incorporation was found to be essential to the nonvolatile memory characteristics and a significant memory window (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FB</sub> ) shift = 6.9 V and charge density = 7.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> at ±8 V gate voltage sweep could be obtained in the sample with satisfied charge retention property. Transmission electron microscopy revealed the nanocomposite layers contain Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te nanocrystals about 5 nm in diameter which may serve as the charge storage traps of memory devices. X-ray photoelectron spectroscopy indicated nitrogen incorporation may alleviate the oxidation of AIST phase and promote the reduction of antimony oxide to form metallic Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te phase in nanocomposite layers, leading to the good nonvolatile memory characteristics of NFGM device containing the AIST-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocomposite as the charge-storage trap layer.

Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application

In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bottom layer. A large memory window and long retention time were obtained. However, the thermal electron excitation is dominant for the electron discharge process during retention. How to reduce the defects in MND layer is important for further improving of memory characteristics.

Enhancement of Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite by Inserting HfO2/SiO2 Blocking Oxide Layer

ABSTRACTThis work presents an enhancement of nonvolatile floating gate memory (NFGM) devices comprised of AgInSbTe (AIST) nanocomposite as the charge-storage trap layer and HfO2 or HfO2/SiO2 as the blocking oxide layer. A significantly large memory window (ΔVFB) shift = 30.7 V and storage charge density = 2.3×1013 cm−2 at ±23V gate voltage sweep were achieved in HfO2/SiO2/AIST sample. Retention time analysis observed a ΔVFB shift about 19.3 V and the charge loss about 13.4% in such a sample under the ±15V gate voltage stress after 104 sec retention time test. Regardless of applied bias direction, the sample containing HfO2/SiO2 layer exhibited the leakage current density as low as 150 nA/cm2 as revealed by the current-voltage (I-V) measurement. This effectively suppresses the electron injection between gate electrode and charge trapping layer and leads to a substantial enhancement of NFGM characteristics.

Retention Characteristics of Schottky Barrier Tunneling Transistor-Nano Floating Gate Memory with Various Side Walls

At present, the nano floating gate memory (NFGM) device has shown a great promise as a ultra-dense, high-endurance memory device for low-power applications. As the size of the NFGM reduced, the short channel effect became one of the critical issues in the base Field Effect Transistor (FET). Schottky barrier tunneling transistor (SBTT) can improve the controllability of the short channel effect. In this work, we studied nano floating gate memory based on the SBTT. Erbium silicide was employed instead of the conventional heavily doped S/D. The NFGM device based on the SBTT used Si nanocrystals as charge storages. The subthreshold slope and the threshold voltage of the SBTT-NFGM were 90 mV/dec. and 0.2 V, respectively. The memory window appeared about 4 V after the applied write/erase bias at +/- 11 V for 500 ms. The write/erase speeds of the memory device were 50 ms and 200 ms at +/- 13 V, respectively. We also analyzed the retention characteristics of the Schottky barrier tunneling transistor nonvolatile floating gate memory according to the various side walls.

Characteristics of AgInSbTe–SiO2 nanocomposite thin film applied to nonvolatile floating gate memory devices

Nanocomposite thin films containing AgInSbTe (AIST) particles embedded in anSiO2 matrix was prepared by sputtering deposition and its feasibility for nonvolatilefloating gate memory (NFGM) was investigated. The sample subjected to a400 °C annealing exhibited a distinct hysteresis memory window(ΔVFB) shift = 6.6 V andcharge density = 5.2 × 1012 cm − 2 after ± 8 V gate voltage sweep. Electrical measurement revealed the current transport is via the Schottkyemission in low applied field and the space-charge-limited conduction mechanism in high appliedfield in the samples, regardless of their thermal history. Transmission electron microscopy andx-ray photoelectron spectroscopy indicated that the metallicSb2Te nanocrystals (NCs) with diameters about 5–7 nm dispersed in a nanocomposite layer may serve as thediscrete charge-storage traps for nonvolatile memory. Analytical results illustrate the utilization of anAIST–SiO2 nanocomposite layer as the core structure of NFGM devices is able to simplify the devicestructure and fabrication process.

Leakage paths identification in NVM using biased data retention

In this paper we propose a way to study leakage paths for electrons during data retention in floating gate non-volatile memories and especially in EEPROM memory cells. We investigate the main leakage paths, through tunnel oxide as well as through the tri-layer stack oxide “oxide/nitride/oxide” (ONO). We used a TCAD simulation of the full EEPROM cell to precisely determine the control gate bias voiding the electric field through ONO or tunnel oxide. Data retention measurements are then performed with simulated bias. We highlight the fact that leakage paths during data retention are different for extrinsic and intrinsic cells. Indeed, extrinsic behavior disappears when voiding electric field across tunnel oxide, showing these cells leak through tunnel oxide, whereas intrinsic behavior is the same whatever the electric field across tunnel oxide, showing charge loss in intrinsic cells is due to another path.

Nonvolatile Floating Gate Memory Devices Containing AgInSbTe-SiO2 Nanocomposite Thin Film Prepared by Sputtering Method

AbstractAgInSbTe (AIST)-SiO2 nanocomposite layer prepared by a one-step sputtering process utilizing target-attachment method was implanted in the nonvolatile floating gate memory (NFGM) devices. Device sample subjected to post annealing at 400°C for 2 min in atmospheric ambient exhibited a significant hysteresis memory window (ΔVFB) shift = 5.91V and charge density = 5.22×12 cm-2 after ±8V voltage sweep. During the retention time test, a ΔVFB shift about 3.50 V and charge loss about 28.4% were observed in the sample after a ±5V voltage stress for 104 sec. Cross-sectional TEM revealed that the nanocomposite layer contains the crystalline AIST nanoparticles with the sizes about 5 to 7 nm embedded in SiO2 matrix. XPS analysis indicated that annealing induces the reduction of antimony oxides to form metallic Sb nanocrystals and suppresses the oxygen defects and charge loss in nanocomposite layer. Analytical results illustrated that the utilization of AIST-SiO2 nanocomposite layer may simplify the preparation of NFGM device with satisfactory electrical properties, implying a promising feasibility of such a nanocomposite layer to NFGM devices.