Non-binary LDPC Research Articles

Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

In this paper, a design approach for architecture- aware nonbinary low-density parity-check convolutional codes (NB-LDPC-CCs) is presented to jointly optimizes the code performance and decoder complexity for achieving high energy-efficiency decoder. The proposed NB-LDPC-CCs not only feature simple structure and low degree, but also compete with other published NB-LDPC-CCs on error-correction capability. With these codes, we present a memory-based layered decoder architecture, where the computation units and the scheduling of the computations are optimized to increase energy efficiency. To demonstrate the feasibility of proposed techniques, a time-varying (50,2,4) NB-LDPC-CC over GF(256) is constructed, and associated decoder is implemented in 90 nm CMOS. The code can reach ${\rm BER}=10^{-5}$ at ${\rm SNR}=0.9 {\rm dB}$ , and support multi code rates with puncturing. Comparing with the state-of-the-art designs, the proposed decoder can save 74% power under the same number of iterations, making it suitable for emerging Internet of Things (IoT) applications.

A low complexity detection/decoding algorithm for NB-LDPC coded PRCPM system

This paper studies the combination of non-binary low-density parity-check (NB-LDPC) codes and M-ary partial response continuous phase modulation (PRCPM). A low-complexity joint detection/decoding algorithm is proposed, which is referred to as the Max-Log-MAP/X-EMS algorithm. In this joint algorithm, the CPM detector is implemented by the Max-Log-MAP algorithm while the LDPC decoder is implemented by the extended min-sum (EMS) algorithms. Three kinds of EMS algorithms, including D-EMS, T-EMS, and M-EMS algorithms, are compared, which are referred to as X-EMS algorithm for convenience. Simulation results show that the Max-Log-MAP/X-EMS algorithm performs as well as the traditional iterative detection/decoding algorithm based on the BCJR algorithm and the q-ary sum–product algorithm, but with lower complexity. In addition, comparison of the proposed NB-LDPC coded PRCPM system with the eBCH coded PRCPM system is given, which shows the performance advantages of our system.

Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes

Nonbinary low-density parity-check (NB-LDPC) codes have become an efficient alternative to their binary counterparts in different scenarios, such as moderate codeword lengths, high-order modulations, and burst error correction. Unfortunately, the complexity of NB-LDPC decoders is still too high for practical applications, especially for the check node (CN) processing, which limits the maximum achievable throughput. Although a great effort has been made in the recent literature to overcome this disadvantage, the proposed decoders are still not ready for high-speed implementations for high-order fields. In this paper, a simplified trellis min–max algorithm is proposed, where the CN messages are computed in a parallel way using only the most reliable information. The proposed CN algorithm is implemented using a horizontal layered schedule. The overall decoder architecture has been implemented in a 90-nm CMOS process for a ( $N=837$ and $K=726$ ) NB-LDPC code over GF(32), achieving a throughput of 660 Mb/s at nine iterations based on postlayout results. This decoder increases hardware efficiency compared with the existing recent solutions for the same code.

Challenges and some new directions in channel coding

Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: Spatially coupled low-density parity-check (LDPC) codes, non-binary LDPC codes, and polar coding.

Multiple-Votes Parallel Symbol-Flipping Decoding Algorithm for Non-Binary LDPC Codes

A novel decoding algorithm for non-binary low density parity check (NB-LDPC) codes is proposed. The algorithm builds on the recently designed parallel symbol-flipping decoding (PSFD) algorithm and combines a technique of error estimation and a method of multiple voting levels from each unsatisfied check-sum to the corresponding variable nodes. Simulations results, performed on a number of NB-LDPC codes of various lengths and column weights constructed using several methods, show that the new algorithm not only avoids using code-dependent voting threshold but also improves the error rate performance of the PSFD algorithm, particularly for low column weight parity-check matrices.

FPGA implementation of concatenated non-binary QC-LDPC codes for high-speed optical transport.

In this paper, we propose a soft-decision-based FEC scheme that is the concatenation of a non-binary LDPC code and hard-decision FEC code. The proposed NB-LDPC + RS with overhead of 27.06% provides a superior NCG of 11.9dB at a post-FEC BER of 10-15. As a result, the proposed NB-LDPC codes represent the strong FEC candidate of soft-decision FEC for beyond 100Gb/s optical transmission systems.

A Matrix-Theoretic Approach to the Construction of Non-Binary Quasi-Cyclic LDPC Codes

This paper presents two simple and very flexible methods for constructing non-binary (NB) quasi-cyclic (QC) LDPC codes. The proposed construction methods have several known ingredients including base array , masking , binary to non-binary replacement , and matrix-dispersion . By proper choice and combination of these ingredients, NB-QC-LDPC codes with excellent performance can be constructed. The constructed codes can be decoded with a reduced-complexity iterative decoding scheme which significantly reduces the hardware implementation complexity.

An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes

This brief presents an area-efficient relaxed half-stochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-error-rate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

Joint sparse graph over GF( q ) for code division multiple access systems

Low-density signature code division multiple access (LDS-CDMA) and low-density parity-check (LDPC) code can both be represented by a single sparse graph. In this study, the authors propose a joint sparse graph (JSG) over GF(q) which combines LDS-CDMA and non-binary LDPC codes, namely JSG-CDMA. On the JSG, multiple accessing and channel coding are well-linked together, in addition, joint detection and decoding are performed by message passing algorithm. Two schedules for message updating on the JSG, that is, flooding and serial schedules, are, respectively, presented. To predict the convergence behaviour of the joint detection and decoding, they depict the iterative structure of the JSG-CDMA receiver and analyse its extrinsic information transfer chart. Key factors of JSG-CDMA include message passing schedule, maximum iteration number and Galois field order. Simulation results show that JSG-CDMA performs much better than conventional CDMA, in addition, compared with LDS-CDMA and turbo structured LDS-CDMA, at a bit error rate of 3 × 10−4, JSG-CDMA brings about 1.9 and 1.1 dB gain, respectively.

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating

Nonbinary LDPC (NB-LDPC) codes, defined over Galois field, offer better coding gain and a lower error floor than binary LDPC codes. However, the complex decoding and large memory requirement have prevented any practical chip implementations. We present a 1.22 Gb/s fully parallel decoder of a GF(64) (160, 80) regular-(2, 4) NB-LDPC code in 65 nm CMOS. The reduced number of edges in NB-LDPC code's factor graph permits a low wiring overhead in the fully parallel architecture. The throughput is further improved by a one-step look-ahead check node design that increases the clock frequency to 700 MHz, and the interleaving of variable node and check node operations that shortens one decoding iteration to 47 clock cycles. We allow each processing node to detect its own convergence and apply dynamic clock gating to save power. When all processing nodes have been clock gated, the decoder terminates and continues with the next input to increase the throughput to 1.22 Gb/s. The dynamic clock gating and decoder termination improve the energy efficiency to 3.03 nJ/b, or 259 pJ/b/iteration, at 1.0 V and 700 MHz. Voltage scaling to 675 mV improves the energy efficiency to 89 pJ/b/iteration for a throughput of 698 Mb/s at 400 MHz.

Nonbinary LDPC Codes on Cages: Structural Property and Code Optimization

A (v,g)-cage is a (not necessarily unique) smallest v-regular graph of girth g. On such a graph, a nonbinary (2,v)-regular low-density parity-check (LDPC) code can be defined such that the Tanner graph has girth 2g and the code length achieves the minimum possible. In this paper, we focus on two aspects of this class of codes, structural property and code optimization. We find that, in addition to those found previously, many cages can be used to construct structured LDPC codes. We show that all cages with even girth can be structured as protograph-based codes, many of which have block-circulant Tanner graphs. We also find that four cages with odd girth can be structured as protograph-based codes with block-circulant Tanner graphs. For code optimization, we develop an ontology-based approach. All possible inter-connected cycle patterns that lead to low symbol-weight codewords are identified to put together the ontology. By doing so, it becomes handleable to estimate and optimize distance spectrum of equivalent binary image codes. We further analyze some known codes from the Consultative Committee for Space Data Systems recommendation and design several new codes. Numerical results show that these codes have reasonably good minimum bit distance and perform well under iterative decoding.

Power Allocation Optimization: Linear Precoding Adapted to NB-LDPC Coded MIMO Transmission

In multiple-input multiple-output (MIMO) transmission systems, the channel state information (CSI) at the transmitter can be used to add linear precoding to the transmitted signals in order to improve the performance and the reliability of the transmission system. This paper investigates how to properly join precoded closed-loop MIMO systems and nonbinary low density parity check (NB-LDPC). Theqelements in the Galois field, GF(q), are directly mapped toqtransmit symbol vectors. This allows NB-LDPC codes to perfectly fit with a MIMO precoding scheme, unlike binary LDPC codes. The new transmission model is detailed and studied for several linear precoders and various designed LDPC codes. We show that NB-LDPC codes are particularly well suited to be jointly used with precoding schemes based on the maximization of the minimum Euclidean distance (max-dmin) criterion. These results are theoretically supported by extrinsic information transfer (EXIT) analysis and are confirmed by numerical simulations.

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes

A one minimum only decoder for Trellis-EMS (OMO T-EMS) and for Trellis-Min-max (OMO T-MM) is proposed in this paper. In this novel approach, we avoid computing the second minimum in messages of the check node processor, and propose efficient estimators to infer the second minimum value. By doing so, we greatly reduce the complexity and at the same time improve latency and throughput of the derived architectures compared to the existing implementations of EMS and Min-max decoders. This solution has been applied to various NB-LDPC codes constructed over different Galois fields and with different degree distributions showing in all cases negligible performance loss compared to the ideal EMS and Min-max algorithms. In addition, two complete decoders for OMO T-EMS and OMO T-MM were implemented for the (837,726) NB-LDPC code over GF(32) for comparison proposals. A 90 nm CMOS process was applied, achieving a throughput of 711 Mbps and 818 Mbps respectively at a clock frequency of 250 MHz, with an area of 19.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 16.10 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after place and route. To the best knowledge of the authors, the proposed decoders have higher throughput and area-time efficiency than any other solution for high-rate NB-LDPC codes with high Galois field order.

Message Quantization Scheme for Nonbinary LDPC Decoder FPGA Implementation

Message Quantization Scheme for Nonbinary LDPC Decoder FPGA Implementation

An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes

Nonbinary low-density parity-check (NB-LDPC) codes outperform their binary counterparts in some cases, but their high decoding complexity is a significant hurdle to their applications. In this paper, we propose a decoding algorithm with reduced computational complexities and smaller memory requirements for NB-LDPC codes. First, a simplified algorithm is proposed to reduce the computational complexity of variable node processing. To reduce the memory requirements, existing NB-LDPC decoders often truncate the message vectors to a limited number n m of values. However, the memory requirements of these decoders remain high when the field size is large. In this paper, an improved trellis-based check node processing algorithm is proposed to significantly reduce the memory requirement. The number of elements in a variable-to-check message is reduced to n v (n v <; n m ). The sorted log likelihood ratio (LLR) vector of a check-to-variable (c-to-v) message is approximated using a piecewise linear function. For each a priori message, most of the LLRs are approximated with a linear function. Two low complexity LLR generation units (LGUs) are proposed to compute LLR vectors for c-to-v messages. A fully parallel NB-LDPC decoder over GF(256) is implemented with 28-nm CMOS technology. The decoder over GF(256) achieves a throughput of 546 Mb/s and an energy efficiency of 0.178 nJ/b/iter.

A coding technique for Q-frequency S-user gaussian channel

The paper addresses the problem of constructing an asynchronous multiple access system for a multiuser Q-frequency channel with additive white gaussian noise (AWGN). To solve the problem we propose a coding scheme for the channel. The major component of the scheme is non-binary low-density parity-check (LDPC) code. To increase the transmission rate we introduce the embedded modulation. The efficiency of the resulting multiple-access system is shown by simulations.

EXIT Chart Analysis of Puncturing for Non-Binary LDPC Codes

This letter presents an EXtrinsic Information Transfer (EXIT) chart tool for the puncturing of non-binary (NB) low-density parity-check (LDPC) codes. With the help of this tool, we study the dependence of the performance of various bitwise and symbolwise puncturing patterns on the degree of a variable node (VN). The grouping algorithm (GA) is a useful technique for the short-length codes to find the recoverable VNs. By incorporating the GA under the EXIT chart model, we propose a method to find the optimum recoverable puncturing pattern.

Towards optimal edge weight distribution and construction of field‐compatible low‐density parity‐check codes over GF( q )

Non-binary low-density parity-check (NB-LDPC) codes can be directly constructed by using algebraic methods, or indirectly constructed by mapping well-designed binary parity-check matrices to non-binary parity-check matrices. Given the Tanner graph (TG) of a NB-LDPC code, the selection of edge weights in the TG significantly affects the performance of the NB-LDPC code. The authors introduce an edge weight distribution (EWD) parameter for the TG of NB-LDPC codes. By utilising particle swarm optimisation (PSO), the EWD is optimised and it has been demonstrated that the optimal EWD approaches a two-element distribution for large field size and high average variable-node degree. With the optimised EWD, the authors construct a class of field-compatible LDPC (FC-LDPC) codes over GF(q) whose parity-check matrices only include elements 0, 1 and 2, and can be encoded and decoded over different field sizes. The simulations demonstrate that the performance of the proposed FC-LDPC codes improves monotonically with increasing field size, and significantly outperforms that of the corresponding algebraic NB-LDPC codes or NB-LDPC codes generated with uniform distribution of non-zero elements over GF(q).

A Hybrid Decoding Scheme for Short Non-Binary LDPC Codes

In this paper, an iterative soft-decision hybrid decoding algorithm for non-binary low-density parity-check (LDPC) codes with short codeword lengths is proposed. The rationale of the approach is to combine the classical belief propagation (BP) iterative LDPC decoding algorithm with the most reliable basis (MRB) decoding algorithm. This allows to achieve significant performance improvements, with a complexity that, for medium/low error rates, is only slightly higher than that of the BP algorithm alone. The performance improvement with respect to pure BP decoding is up to 0.7 dB at codeword error rate (CER) ≈ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> . Notably, for a fixed MRB order, hybrid decoding achieves a gain up to 0.5 dB at CER ≈ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> with respect to BP decoding and MRB decoding used alone.