Nonzero Bit Research Articles

SOFTWARE/HARDWARE CO-DESIGN OF MODULAR EXPONENTIATION FOR EFFICIENT RSA CRYPTOSYSTEM

This paper presents an implementation of Rivest, Shamir and Adleman (RSA) cryptosystem based on hardware/software (HW/SW) co-design. The main operation of RSA is the modular exponentiation (ME) which is performed by repeated modular multiplications (MMs). In this work, the right-to-left (R2L) algorithm is used for the implementation of the ME as a programmable system on chip (PSoC). The processor MicroBlaze of Xilinx is used for flexibility. The R2L method is often suggested to improve the timing performance, since it is based on parallel computations of MMs. However, if the optimization of HW resources is a constraint, this method can be executed sequentially using a single modular multiplier as a custom intellectual property (IP). Consequently, the execution time of the ME becomes dependent of three factors, namely the capability of the custom IP to perform the MMs, the nonzero bit string of the exponent and the communication link between the processor and the custom IP. In order to achieve the best trade-off between area, speed and flexibility, we propose three implementations in this work. The first one is a pure software solution. The second one takes benefit of a HW accelerator dedicated to the MM execution. The last one is based on a dual strategy. Two parallel MMs are implemented within a custom IP and local memories are used close to the arithmetic units to minimize the communication link influence. The results show that in the application to RSA 1024-bits, the ME runs in 22,25 ms, while using only 1,848 slices.

UD(Ultra Definition) 동영상 실시간 처리를 위한 H.264/AVC CAVLC 병렬 아키텍처 설계

본 연구에서는 UHD(3840×2160)영상을 실시간 처리하는 고성능 H.264/AVC CAVLC 부호화기를 설계하였다. 연산처리 성능을 높이기 위해 통계값 탐색 과정과 코드워드 부호화 과정을 각각 1사이클에 처리하도록 설계하였다. 통계값 탐색과정을 1사 이클에 처리하기 위해 16개 계수들의 ‘0’ 또는 ‘0’이 아님을 표시하는 비트열을 만들어 산술 및 논리연산을 통해 통계값을 한번에 구하였다. 그리고 코드워드 부호화 과정을 1사이클에 처리하기 위해 레벨의 코드워드 길이를 결정하는 계수들과 임계값들과의 비교 연산을 동시에 처리함으로써 코드워드 부호화 과정의 재귀적 연산을 제거하였다. 제안하는 H.264/AVC 병렬 CAVLC 부호화기는 통계값 탐색 단계과 코드워드 부호화 단계로 나뉘는 2단 파이프라인 구조로 고속 병렬 연산 회로를 구현 하였으며, 산술 연산을 적용하여 코드워드 부호화 테이블을 회로의 크기를 줄이고자 하였다. 0.13um 공정에서 시뮬레이션한<BR>결과, 게이트 수는 33.4Kgates이며, 최대동작주파수 100MHz에서 UD 영상을 초당 100프레임으로 실시간 처리가 가능하다.

Optimized Packet Size Selection in Underwater Wireless Sensor Network Communications

In this paper, we investigate the effect of packet size selection on the performance of media access control (MAC) protocols for underwater wireless sensor networks, namely, carrier sense multiple access (CSMA) and the distance-aware collision avoidance protocol (DACAP). Our comparative analysis, conducted via ns-2 simulations, considers scenarios with varying, nonzero bit error rate (BER) and interference. We investigate metrics such as throughput efficiency (the ratio between the delivered bit rate and the offered bit rate), end-to-end packet latency, measured “per meter” to allow for different sizes of deployment areas, and the energy consumed to correctly deliver an information bit to the network collection point. Our results show the dependence of these metrics on the packet size, indicating the existence of an optimum. The optimum packet size is found to depend on the protocol characteristics, the bit rate, and the BER. For each protocol and scenario considered, we determine the packet size that optimizes throughput performance, and we show its effect on the normalized packet latency and on energy consumption.

Service Differentiation Schemes in IEEE 802.11 Wireless LANs with Variable Frame Size

Service differentiation in wireless LANs is a growing demand, because of their increasing use for applications with different QoS requirements. This paper analyzes IEEE 802.11e based service differentiation schemes—specifically, differentiating minimum back-off window size, the retransmission limit, and combination of the two— in the presence of channel error. An analytical model is developed that can be used to compute performance measures such as saturation throughput, saturation delay, and frame dropping probabilities of different priority classes, in the presence of channel error. The effect of frame size, the number of contention nodes, transmission collision probability, and channel error conditions on the above-mentioned performance measures are studied. The analysis applies to both basic access and RTS/CTS mechanisms. A model to evaluate the performance under a hybrid access scheme, a mechanism in which both basic access and RTS/CTS mechanisms coexist, is also proposed. The frame lengths are assumed to have a general distribution F(A). It is found that in a channel with nonzero bit error rate (BER), there exists an optimal frame size that maximizes the throughput. This optimal frame size reduces with increase in BER, and is independent of the number of contending nodes.

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 μm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

Minimal-memory bit-vector architecture for computational mathematical morphology using subspace projections

Computational mathematical morphology (CMM) is a nonlinear filter representation particularly amenable to real-time image processing. A windowed, translation-invariant filter is represented by a set of less-than-or-equal decisions that are executed by a parallel arrangement of comparators. In the state-of-the-art implementation, each pixel value of a windowed observation is indexed into separate lookup tables to retrieve a set of bit vectors which are "anded" together to produce a bit vector with a unique nonzero bit. The position of that bit is used to look up a filter value in a table. The number of stored bit vectors is proportional to the number of image gray levels. An architecture for CMM is presented that uses a minimal number of bit vectors so that required memory is less sensitive to the number of gray levels. The number of pixels in the observation window is the dimension of the image space. In the proposed architecure, basis elements are projected to subspaces of the image space and only bit vectors unique to each subspace are stored. Each projection corresponds to a subspace partition. Filter memory is greatly reduced by using intermediate lookup tables to map observations to unique bit vectors. We investigate two possible projection strategies: A fixed, singleton architecture, in which each subspace is one dimension, and a minimal architecture, in which a large number of subspace projections are searched for, one with minimal memory. Insensitivity to the number of gray levels is demonstrated through simulated, random-image space tessellations. We also present memory savings in a digital photocopier application.

On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods

The most computationally intensive part of a wideband receiver is the channelizer. The computational complexity of linear phase finite impulse response (LPFIR) filters employed in the channelizer is dominated by the number of adders used in the implementation of the multipliers. In this paper, two methods are proposed to efficiently implement the channel filters in a wideband receiver based on common subexpression elimination (CSE). We exploit the fact that a significant amount of redundant multiplications exist in the filter-bank channelizer as it extracts multiple narrowband channels from the wideband signal. By forming three and four nonzero-bit super-subexpressions utilizing redundant identical shifts that exist between a two- nonzero-bit common subexpression (CS) and a third nonzero bit, or between two nonzero-bit CS, the number of adders to implement the channel filters can be reduced considerably. Furthermore, the complexity of the adders is analyzed and design examples of the channel filters employed in the digital advanced mobile phone system (D-AMPS) and the personal digital cellular (PDC) channelizers show that the proposed methods offer considerable reduction in the number of full adders when compared to conventional CSE methods.

Bit vector architecture for computational mathematical morphology

A real-time, compact architecture is presented for translation-invariant windowed nonlinear discrete operators represented in computational mathematical morphology. The architecture enables output values to be computed in a fixed number of operations and thus can be pipelined. Memory requirements for an operator are proportional to its basis size. An operator is implemented by three steps: 1) each component of a vector observation is used as an index into a table of bit vectors; 2) all retrieved bit vectors are "ANDed" together; and 3) the position of the first nonzero bit is used as an index to a table of output values. Computational mathematical morphology is described, the new architecture is illustrated through examples, and formal proofs are given. A modification of the basic architecture provides for increasing operators.

A novel design of a two operand normalization circuit

This paper presents a new design for two operand normalization. The two operand normalization operation involves the normalization of at least one of two operands by left shifting both by the same amount. Our design performs the computation of the shift by making an OR of the bits of both operands in a tree network, encoding the position of the first nonzero bit. The encoded position is obtained most significant bit first, and then there is an overlapping with the shifting operation. The design we propose replaces two leading zero detector circuits and a comparator, that are present in the conventional approach. Our scheme demonstrates to be more area efficient than the conventional one. The circuit we propose is useful in floating point complex multiplication and COordinate Rotation DIgital Computer (CORDIC) processors.

Capacity of digital communication system with allowed nonzero error rate

Where a nonzero bit error rate can be tolerated in a communications system then the maximum possible bit rate is greater than the channel capacity. Compensating for the error rate is simple. If the error rate is below 10-3 then the effect is insignificant.

Tactical Configurations and Their Generic Ring

A construction of Tits is used to cast the argument of Kilmoyer-Solomon and Higman proving the Feit-Higman theorem in the context of tactical configurations. An analog of a result of Cvetkovic shows what combinatorial data is needed to determine the representations associated with a given configuration. The possible representations fall into three types. A bound is given for the size of certain configurations for which one of the three types fails to occur and for which the first non-zero bit of combinatorial data is sufficiently large.

On combined symbol-and-bit error-control [4,2] codes over&lt;tex&gt;{0,1}^8&lt;/tex&gt;to be used in the

The construction, properties, and decoding of four nonequivalent <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4,2]</tex> codes over the alphabet <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">{0,1}^{8}</tex> are described. These codes are able to correct the following error patterns: <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1)</tex> error patterns containing one nonzero byte, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2)</tex> error patterns containing up to three nonzero bits, and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3)</tex> error patterns containing one byte erasure and at most one nonzero bit. In addition, all error patterns containing one byte erasure and two nonzero bits can be detected. These codes can be used in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"/>

An Analysis of a TDMA Channel Using Stop-and-Wait, Block, and Select-and-Repeat ARQ Error Control

In this paper, the multiaccess broadcast communication channel operating under a TDMA control discipline and employing an ARQ scheme is examined. The generating function of the message delay distribution is derived. The effects of nonzero bit error rates on multipacket messages under several stop-and-wait and block ARQ systems are incorporated. Numerical results for the steady-state mean and variance of the message delay are presented for a stationary transmission error process model in which errors occur as independent events. Results for this channel under a select-and-repeat ARQ system are developed for single packet messages. Stability requirements are stated, useful bounds on the average message delay at steady state are derived, and numerical examples are presented.