Non-volatile Storage Research Articles

Heterogeneous Integration of Atomically Thin Semiconductors for Non-von Neumann CMOS.

Atomically thin, 2D, and semiconducting transition metal dichalcogenides (TMDs) are seen as potential candidates for complementary metal oxide semiconductor (CMOS) technology in future nodes. While high-performance field effect transistors (FETs), logic gates, and integrated circuits (ICs) made from n-type TMDs such as MoS2 and WS2 grown at wafer scale have been demonstrated, realizing CMOS electronics necessitates integration of large area p-type semiconductors. Furthermore, the physical separation of memory and logic is a bottleneck of the existing CMOS technology and must be overcome to reduce the energy burden for computation. In this article, the existing limitations are overcome and for the first time, a heterogeneous integration of large area grown n-type MoS2 and p-type vanadium doped WSe2 FETs with non-volatile and analog memory storage capabilities to achieve a non-von Neumann 2D CMOS platform is introduced. This manufacturing process flow allows for precise positioning of n-type and p-type FETs, which is critical for any IC development. Inverters and a simplified 2-input-1-output multiplexers and neuromorphic computing primitives such as Gaussian, sigmoid, and tanh activation functions using this non-von Neumann 2D CMOS platform are also demonstrated. This demonstration shows the feasibility of heterogeneous integration of wafer scale 2D materials.

Robust and Programmable Logic-In-Memory Devices Exploiting Skyrmion Confinement and Channeling Using Local Energy Barriers

Magnetic skyrmions are promising candidates for logic-in-memory applications, intrinsically merging high density non-volatile data storage with computing capabilities, owing to their nanoscale size, fast motion, and mutual repulsions. However, concepts proposed so far suffer from reliability issues as well as inefficient conversion of magnetic information to electrical signals. In this paper, we propose a logic-in-memory device which exploits skyrmion confinement and channeling using anisotropy energy barriers to achieve reliable data storage and synchronous shift in racetracks combined with cascadable and reprogrammable logics relying purely on magnetic interactions. The device combines a racetrack shift register based on skyrmions confined in nanodots with Full Adder (FA) gates. The designed FA is reprogrammable and cascadable and can also be used to perform simple logic operations such as AND, OR, NOT, NAND, XOR and NXOR. The monolithic design of the logic gate and the absence of any complex electrical contacts makes the device ideal for integration with conventional CMOS circuitry.

Room-Temperature Fabricated Multilevel Nonvolatile Lead-Free Cesium Halide Memristors for Reconfigurable In-Memory Computing.

Recently, conductive-bridging memristors based on metal halides, such as halide perovskites, have been demonstrated as promising components for brain-inspired hardware-based neuromorphic computing. However, realizing devices that simultaneously fulfill all of the key merits (low operating voltage, high dynamic range, multilevel nonvolatile storage capability, and good endurance) remains a great challenge. Herein, we describe lead-free cesium halide memristors incorporating a MoOX interfacial layer as a type of conductive-bridging memristor. With this design, we obtained highly uniform and reproducible memristors that exhibited all-around resistive switching characteristics: ultralow operating voltages (<0.18 V), low variations (<30 mV), long retention times (>106 s), high endurance (>105, full on/off cycles), record-high on/off ratios (>1010, smaller devices having areas <5 × 10-4 mm2), fast switching (<200 ns), and multilevel programming abilities (>64 states). With these memristors, we successfully implemented stateful logic functions in a reconfigurable architecture and accomplished a high classification accuracy (ca. 90%) in the simulated hand-written-digits classification task, suggesting their versatility in future in-memory computing applications. In addition, we exploited the room-temperature fabrication of the devices to construct a fully functional three-dimensional stack of memristors, which demonstrates their potential of high-density integration desired for data-intensive neuromorphic computing. High-performance, environmentally friendly cesium halide memristors provide opportunities toward next-generation electronics beyond von Neumann architectures.

Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator

With growing on-device IoT processing, security on edge devices becomes increasingly important. Among Trusted Execution Environment (TEE), an open-source RISC-V Keystone TEE is the expected one. However, some issues remain when applying it to various devices: untrusted DRAM, and untrusted path to non-volatile storage. These issues can be resolved by Memory Protection Engine (MPE) based on an integrity tree, and Non-Volatile Main Memory (NVMM), respectively. TEE, MPE, and NVMM must be cooperatively optimized to exploit performance. Despite this demand, there is no widely available platform which enables fast, reliable, and system-wide evaluation. In the paper, we provide an open-source hardware simulator for secure edge devices. We implemented an MPE using SGX-style Integrity Tree on the Keystone compatible RISC-V SoC. Then, we ported the NVMM simulation technique to it. Its whole design was publicized to widely provide a baseline hardware design. The MPE behavior was validated by using micro benchmarks. It revealed that the MPE read/write overhead is <inline-formula><tex-math notation="LaTeX">$2.55\times /4.16\times$</tex-math></inline-formula> on DRAM, and <inline-formula><tex-math notation="LaTeX">$3.05\times /5.40\times$</tex-math></inline-formula> on NVMM, respectively. Besides, we discuss our work's role by comparing with the gem5 considering TEE evaluation time and impact of the protected NVMM.

Memory analysis of .NET and .Net Core applications

Memory analysis is a digital forensics technique whose goal is to model a computer system's state based solely on the analysis of a snapshot of physical memory (RAM). Memory forensics is frequently employed in incident response to detect and analyze modern malware and attack frameworks. Memory forensics is a particularly powerful tool for analyzing modern malware, which may exist only in memory and not touch non-volatile storage. Memory-only attacks leave no trace of the malware and its associated modules on the file system and all data that traverses the network is commonly encrypted. While initially focused on kernel level rootkits, memory analysis research efforts have recently shifted to detection of userland malware. This shift occurred as operating system vendors have strongly locked down the ability for kernel rootkits to load, and, in turn, malware authors have developed significant userland malware capabilities. In this paper, we present our effort to develop memory analysis capabilities that target a very powerful and widely abused set of userland runtimes: the .NET Framework and its replacement, .NET Core. To support automated and repeatable results, even for non-expert investigators, we developed a number of Volatility plugins that automatically target key areas of these runtimes and report any suspicious artifacts. Our suite of new plugins provides investigators with deep insight into the use of .NET on a target system as well as identification of suspicious and malicious components. These capabilities considerably advance a defenders' ability to combat, contain, and understand modern malware.

A Stable Low Power Dissipating 9 T SRAM for Implementation of 4 × 4 Memory Array with High Frequency Analysis

Today’s high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals.

Structural optimization of integrated non-volatile photonic memory towards high storage density and low energy consumption

Photonic memory provides optics the opportunity for upgrading data storage hardware and shows great promise in future computing hardware due to its innate superiority in speed, power consumption and bandwidth. Chalcogenide phase-change materials (PCMs) such as Ge2Sb2Te5 (GST) are one of the most promising non-volatile storage materials and have been used for on-chip photonic integration circuits (PIC). Here, we explore the transmission contrast and the thermal distribution produced by different spatial structures of GST cells in photonic memory including geometric shapes, vertical positions and array distributions. We design the geometric shape of GST cells in photonic memory that matches the optical field distribution profile, causing a more than 20% increase in transmission contrast. We then set the vertical position of GST cells embedded in waveguides where the GST cell is overlapping most with the waveguide propagation mode, increasing the transmission contrast by more than 50%. Engineering the surrounding cladding layer is also an effective method to improve the transmission contrast (&gt;10%). Beyond that, selecting a suitable size of the gap can obtain a better balance between the storage capacity and the thermal management in uniform GST arrays while the non-uniform array can further improve the thermal uniformity. Our studies indicate that spatial distribution optimization of light storage media is necessary to develop low-energy-consumption on-chip PIC.

Stable Resistive Switching in ZnO/PVA:MoS2 Bilayer Memristor.

Reliability of nonvolatile resistive switching devices is the key point for practical applications of next-generation nonvolatile memories. Nowadays, nanostructured organic/inorganic heterojunction composites have gained wide attention due to their application potential in terms of large scalability and low-cost fabrication technique. In this study, the interaction between polyvinyl alcohol (PVA) and two-dimensional material molybdenum disulfide (MoS2) with different mixing ratios was investigated. The result confirms that the optimal ratio of PVA:MoS2 is 4:1, which presents an excellent resistive switching behavior. Moreover, we propose a resistive switching model of Ag/ZnO/PVA:MoS2/ITO bilayer structure, which inserts the ZnO as the protective layer between the electrode and the composite film. Compared with the device without ZnO layer structure, the resistive switching performance of Ag/ZnO/PVA:MoS2/ITO was improved greatly. Furthermore, a large resistive memory window up to 104 was observed in the Ag/ZnO/PVA:MoS2/ITO device, which enhanced at least three orders of magnitude more than the Ag/PVA:MoS2/ITO device. The proposed nanostructured Ag/ZnO/PVA:MoS2/ITO device has shown great application potential for the nonvolatile multilevel data storage memory.

A Nonvolatile Multilevel Data Storage Memory Based on Two-Dimensional Materials for Aerospace Applications

Two-dimensional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Se <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> based nonvolatile memories with planar structure can share electrodes in the plane and avoid the crosstalk in the three-dimensional integration, which promotes realizing low-energy-consumption, high-density, low-weight and high-speed devices used for the aerospace. However, the nonvolatile multilevel data storage memory performance on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Se <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is rarely investigated. What’s more, the reliability of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Se <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> based nonvolatile multilevel data storage memories should be considered before they are used in the aerospace. In this work, the nonvolatile multilevel data storage behavior of a planar device based on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Se <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> is demonstrated, and the radiation resistance of the planar device is investigated further. Six states are achieved in the device, and the initial highest ON/OFF ratio is high to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.31 \times 10^{4}$ </tex-math></inline-formula> %. And with good reliability, these six states can be maintained for a long time. Although the nonvolatile multilevel data storage behavior decreases with the increasing irradiation fluence because of the displacement radiation effect, the planar device can still be used as nonvolatile multilevel data storage memory with good readout and retention performance when the irradiation fluence does not exceed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.4 \times 10^{14}$ </tex-math></inline-formula> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The high radiation resistance and stability evidences that the nonvolatile multilevel data storage memory based on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha $ </tex-math></inline-formula> -In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Se <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> nanoflake is competitive in the future application of aerospace.

Systematic Evolution of Optical Bandgap and Local Chemical State in Transparent MgO and HfO2 Resistive Switching Materials

Herein, a comprehensive investigation into the optical, local chemical state, and electrical properties of the less explored magnesium oxide (MgO) are presented for resistive switching data storage applications in reference to the well‐documented hafnium oxide (HfO2). The observed local chemical state from X‐ray photoelectron spectroscopy (XPS) analysis yields a nonlattice oxygen peak in O 1s spectra, indicating the resistive switching potential of polycrystalline MgO analogous to the amorphous HfO2 as‐deposited thin films. The optical investigation through UV–visible spectroscopic and photoluminescence examination reveals the high transmissivity of HfO2 (84–98%) and MgO (86–88%) thin films in visible and near‐infrared domains, with a high bandgap of 5.6 and 4.2 eV, respectively, implying the possibility of two distinct stable states essential for resistive switching phenomena. Additionally, the electrical characterization manifests bipolar switching phenomena in HfO2 and MgO metal–oxide–metal stacks with SET transitions at 0.6 and 0.5 V, followed by RESET transitions at −0.6 and −0.5 V, respectively. Both oxides in respective stacks exhibit dominant Ohmic conduction in high‐resistive and low‐resistive regions during positive and negative bias. These observations propose MgO as a preferable resistive switching material for nonvolatile data storage applications, showing similar properties of widely studied HfO2.

Fast switching of magnetic vortex state under an alternating magnetic field

Vortex is considered to be a promising candidate for nonvolatile magnetic random storage devices due to its unique binary state and high thermal stability. The control of vortex polarity and chirality is key to devices based on vortex. In this work, the switching of the magnetic vortex state in Permalloy nanodisks has been investigated by micromagnetic simulation employing in-plane alternating magnetic fields. During the switching of magnetic vortex state, an antivortex is formed, and the antivortex and vortex will not annihilate together. The formation of antivortex and the annihilation of initial vortex lead to the switching of magnetic vortex state. The switching of vortex state depends on magnetic field and disk size. The switching time of magnetic vortex state declines with the enhancement of magnetic field amplitude or magnetic field frequency. All the switching can be completed within 1.4 ns, indicating that the alternating magnetic field driving can induce the rapid switching of vortex state. This work provides an effective method for the fast switching of magnetic vortex state, which benefits the potential storage applications in vortex-based spintronic devices.

Annihilation dynamics of magnetic skyrmion lattice state under in-plane magnetic field and spontaneous recovery after field removal

Nanoscale magnetic skyrmions are potential candidates for information carriers, for which the nonvolatility under external stimuli is critical to the stability of recorded bits. Here, we present a micromagnetic study on the annihilation dynamics of a two-dimensional skyrmion lattice under a transverse magnetic field and the recoverability of the topological charge after removing the field. The temporal and spatial correlation functions and their Fourier transforms of the spin system reveal position-dependent dynamics under the transverse field. The slow modes $(&lt;10\phantom{\rule{0.16em}{0ex}}\mathrm{GHz})$ hosted by all spins determine the spin configurations, and the fast ones $(&gt;10\phantom{\rule{4pt}{0ex}}\mathrm{GHz})$ around the skyrmion core region control the dynamics of topological properties. A dynamic critical time ${t}_{\mathrm{cri}}$, when the field-induced ferromagnetic nuclei begin to be long-range correlated, is proved by statistical analyses of their spatial distribution over time. If turning off the transverse field before ${t}_{\mathrm{cri}}$, the collective motion of the spin system can restore the previously lost topological charge. Our results guide the realization of nonvolatile information storage in skyrmion lattice, thus widening the possibility of skyrmion-based devices for future spintronics-based nanocomputing.

High-Speed Nanoscale Ferroelectric Tunnel Junction for Multilevel Memory and Neural Network Computing.

Ferroelectric tunnel junction (FTJ) is one promising candidate for next-generation nonvolatile data storage and neural network computing systems. In this work, the high-performance 50 nm-diameter Au/Ti/PbZr0.52Ti0.48O3 (∼3 nm, (111)-oriented)/Nb:SrTiO3 (Nb: 0.7 wt %) FTJs are achieved to demonstrate the scaling down capability of FTJ. As a nonvolatile memory, the FTJ shows eight distinct resistance states (3 bits) with a large ON/OFF ratio (>103), and these states can be switched at a fast speed of 10 ns. Intriguingly, the long-term potentiation/depression and spike timing-dependent plasticity, that is, fundamental functions of biological synapses, can be emulated in the nanoscale FTJ-based artificial synapse. A convolutional neural network (CNN) simulation is then carried out based on the experimental results, and a high recognition accuracy of ∼93.8% on fashion product images is obtained, which is very close to the result of ∼94.4% by a floating-point-based CNN software. In particular, the FTJ-based CNN simulation also exhibits robustness to input image noises. These results indicate the great potential of FTJ for high-density information storage and neural network computing.

Photonic-Crafting of Non-Volatile and Rewritable Antiferromagnetic Spin Textures with Drastic Difference in Electrical Conductivity.

Antiferromagnetic spintronics is an emerging field of non-volatile data storage and information processing. The zero net magnetization and zero stray fields of antiferromagnetic materials eliminate interference between neighbor units, leading to high-density memory integrations. However, this invisible magnetic character at the same time also poses a great challenge in controlling and detecting magnetic states in antiferromagnets. Here, two antiferromagnetic spin states close in energy in strained BiFeO3 thin films at room temperature are discovered. It can be reversibly switched between these two non-volatile antiferromagnetic states by a moderate magnetic field and a non-contact optical approach. Importantly, the conductivity of the areas with each antiferromagnetic textures is drastically different. It is conclusively demonstrated the capability of optical writing and electrical reading of these newly discovered bistable antiferromagnetic states in the BiFeO3 thin films.

Ultrahigh-Speed In-Memory Electronics Enabled by Proximity-Oxidation-Evolved Metal Oxide Redox Transistors.

The pursuit of a universal device that combines nonvolatile multilevel storage, ultrafast writing/erasing speed, nondestructive readout, and embedded processing with low power consumption demands the development of innovative architectures. Although thin-film transistors and redox-based resistive-switching devices have independently been proven to be ideal building blocks for data processing and storage, it is still difficult to achieve both well-controlled multilevel memory and high-precision ultrafast processing in a single unit, even though this is essential for the large-scale hardware implementation of in-memory computing. In this work, an ultrafast (≈42ns) and programable redox thin-film transistor (ReTFT) memory made of a proximity-oxidation-grown TiO2 layer is developed, which has on/off ratio of 105 , nonvolatile multilevel analog storage with a long retention time, strong durability, and high reliability. Utilizing the proof-of-concept ReTFTs, circuits capable of performing fundamental NOT, AND, and OR operations with reconfigurable logic-in-memory processing are developed. Further, on-demand signal memory-processing operations, like multi-terminal addressable memory, learning, pattern recognition, and classification, are explored for prospective application in neuromorphic hardware. This device, which operates on a fundamentally different mechanism, presents an alternate solution to the problems associated with the creation of high-performing in-memory processing technology.

Improved Multibit Storage Reliability by Design of Ferroelectric Modulated Antiferroelectric Memory

In this article, we presented a new concept of ferroelectric (FE) modulated antiferroelectric (AFE) memory with independent two-step state switching and large polarization as a promising option for multibit storage in advanced technology nodes. Based on the Landau–Ginzburg–Devonshire (LGD) theory, four nonvolatile states of AFE with the built-in field can be obtained, and the step-by-step switching among four states was successfully simulated through pulse engineering; then, stable nonvolatile 2-bit storage was experimentally demonstrated in FE/AFE/FE capacitor device, and 0.97-MV/cm bipolar built-in field introduced by FE polarization switching was extracted. The FE + AFE device showed double-peak coercive electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{c}$ </tex-math></inline-formula> ) distribution and large remanent polarization ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{r}$ </tex-math></inline-formula> ) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.9 ~\mu \text{C}$ </tex-math></inline-formula> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with good process stability. Finally, benefitting from the independently step-by-step switching and large density of effective FE domain, the improved multibit storage reliability was verified by kinetic Monte Carlo (KMC) modeling compared to conventional multibit technology.

A novel tunable two dimensional ferroelectric material SbAs(CH2OCH3)2 with topological and valley polarized properties

In recent years, two-dimensional (2D) materials that have ferroelectric, valley polarization as well as topological order is a major focal topic of nanomaterials research. We studied the monolayer (ML) SbAs(CH2OCH3)2 based on first-principles calculations. The adsorption energy results and phono spectra results show that the structure are stable. The in-plane ferroelectricity can be adjusted by rotating functional groups, CH2OCH3-. Chosen a suitable substrate (for example, diagonal boron nitride), an in-plane electric field can be supplied to control the ferroelectric switch. The topological order can be adjusted by stress stretching. After 6% tensile stress, it represents the quantum spin Hall effect. Considering energy band of spin polarization, it shows that the spin-splitting Dirac states at the K and -K valleys have opposite spin moments. The discovery of coexisting ferroelectric, valley polarization and topology in functional 2D materials opens a way for non-volatile memory storage and spintronics applications.

Programmable Terahertz Metamaterials with Non‐Volatile Memory (Laser Photonics Rev. 16(4)/2022)

Programmable Memory Metamaterials In article number 2100472, Benwen Chen, Jingbo Wu, Biaobing Jin, and colleagues present a programmable terahertz metamaterial with memory function. Each pixel is electrically addressable by suppressing the thermal crosstalk, and modulation speed of 1 kHz is obtained. Its state enables being written, read, and erased with an electrical pulse; thus, the non-volatile storage of multi-state terahertz images is demonstrated.

Boolean Logic Function Realized by Phase-Change Blade Type Random Access Memory

Phase-change random access memory (PCRAM) has been considered as one of the most promising candidates for future nonvolatile storage applications. Recent advent of the blade-type PCRAM further shed a light on its commercial prospect due to its much smaller energy consumption than the conventional Lance-type PCRAM. However, the logic computing capability of the blade-type PCRAM remains vague up-to-date. To deeply study its function versatility, we developed a comprehensive three-dimensional model based on the classical nucleation-growth theory to mimic the crystallization and amorphization processes of the blade-type PCRAM device. According to this well-established model, the device resistance after phase transformation was calculated with respect to different crystallization and amorphization pulses. By pertaining high and low pulse magnitudes and device resistances to appropriate input and output logic levels, a variety of Boolean logic functions, including &#x201C; NAND,&#x201D; NOR,&#x201D; AND,&#x201D; OR,&#x201D; and &#x201C; NOT,&#x201D; were successfully achieved on one single PCRAM cell. The feasibility of simultaneously realizing storage and logic computing functions on the designed PCRAM device was therefore demonstrated. Such intriguing merit, combined with its superb storage traits, makes the proposed blade-type PCRAM cell suitable for current in-memory computing and neuromorphic circuits as the key components of future digital computers operated on non-von Neumann mode.

Transparent Asynchronous Parallel I/O Using Background Threads

Moving toward exascale computing, the size of data stored and accessed by applications is ever increasing. However, traditional disk-based storage has not seen improvements that keep up with the explosion of data volume or the speed of processors. Multiple levels of non-volatile storage devices are being added to handle bursty I/O, however, moving data across the storage hierarchy can take longer than the data generation or analysis. Asynchronous I/O can reduce the impact of I/O latency as it allows applications to schedule I/O early and to check their status later. I/O is thus overlapped with application communication or computation or both, effectively hiding some or all of the I/O latency. POSIX and MPI-I/O provide asynchronous read and write operations, but lack the support for non-data operations such as file open and close. Users also have to manually manage data dependencies and use low-level byte offsets, which requires significant effort and expertise to adopt. In this article, we present an asynchronous I/O framework that supports all types of I/O operations, manages data dependencies transparently and automatically, provides implicit and explicit modes for application flexibility, and error information retrieval. We implemented these techniques in HDF5. Our evaluation of several benchmarks and application workloads demonstrates it effectiveness on hiding the I/O cost from the application.