Non-Volatile Memory Express Research Articles

Design and Implementation of Optical Fiber SSD Exploiting FPGA Accelerated NVMe

Missions, both near Earth and deep space, are under consideration that will require data recorder capacities doubled at a rate of approximately every three years. This challenge for ever-increasing mass storage also exists in other applications, such as unmanned aerial vehicle (UAV) and echo recording for phased array radar (PAR). All these scenarios call for storage devices with larger capacity, higher I/O bandwidth, lower latency and smaller size. In this paper, we combine Field Programmable Gate Array (FPGA)-based efficient cores of the emerging Non-Volatile Memory express (NVMe) protocol with Flash storage to improve the I/O bandwidth and latency from the operating system (OS) storage I/O software stack. We provide an alternating operation scheme to guarantee consistency of I/O bandwidth. The device has two independent optical fiber channels to ensure the reliability of interconnections and four NVMe flash storage recording data respectively at the same time, which increase its integration and scalability. The prototype has a capacity of 8TB and a volume of only 990 cubic centimeter, weighing only 2.2 pounds. Experimental results demonstrate that the continuous I/O bandwidth of each channel is above 1GBps with variance no more than 7% for its total capacity, and NVMe host logic core achieves up to 88% lower latency against the OS-based system.

HMB-SSD: Framework for Efficient Exploiting of the Host Memory Buffer in the NVMe SSD

Host Memory Buffer (HMB) is a highlighted feature of the Non-Volatile Memory Express (NVMe) protocol, which is the state-of-the-art storage interface for emerging storage devices such as Solid-State Drives (SSDs). HMB enables the underlying storage to make use of a portion of host memory for caching their address mapping information and/or user data, so that they can overcome the limited capacity of memory within the storage. This technology opens an opportunity to optimize the I/O performance cost-effectively by sharing the ample host memory with the severely resource-constrained device. However, it is challenging to study the HMB-based optimization techniques in the practical system because there is no SSD development platform supporting the HMB feature as well as the commercial SSD products veil their internals, not allowing a custom extension. Motivated by this limitation, this paper presents an HMB-supported SSD development platform called HMB-SSD, which is built by faithfully extending an open-source SSD emulator. HMB-SSD enables to easily integrate and evaluate I/O techniques for the HMB feature in an SSD emulator, which closely mimics the behavior of real devices. We demonstrate the proper operation of our platform and the efficacy of the HMB feature with a case study on write buffering. In our empirical study, the SSD storage achieves a large performance benefit with the HMB-based write buffer, yielding up to 86.2% better performance than that of without it.

Thermal Analysis of Ball Grid Array Non-Volatile Memory Express Solid-State Drive in Vacuum

Solid-state drives (SSDs) have been widely used in data storage for micro satellites, data centers, and mobile products due to their high performance and high reliability. Recently, Samsung Electronics starts to introduce a ball grid array (BGA) non-volatile memory express (NVMe) SSD, which is a combined package of controller and memory units (i.e., DRAM and NAND) into one package. Due to the smaller form factor with high storage densities and multi-functional devices of BGA NVMe SSDs, a thermal issue becomes more important, requiring fundamental understanding of heat dissipation mechanism. Moreover, for applications in micro satellites, thermal analysis of SSDs should be conducted in vacuum environment. Here, we investigate the heat dissipation mechanism in the newly developed BGA NVMe SSD in both the atmosphere and high-vacuum conditions. A finite-element-method-based numerical model is developed for the heat transfer analysis and is verified by experiments at various workload conditions.

An Asynchronous Two-Level Checkpointing Method to Solve Adjoint Problems on Hierarchical Memory Spaces

The problem of data reversal in discretized adjoint problems is often solved using checkpointing, trading memory usage with computations and data movement. The authors present a useful model to design and implement an asynchronous two-level checkpointing method with parameterizable values for current and future system configurations. They also evaluate the benefits of new supercomputing hardware through the implementation of an asynchronous algorithm that takes advantage of the fast NVLINK interconnect and Non-Volatile Memory Express (NVMe) memory. They show that the new hardware combined with an asynchronous approach is able to run bigger simulations faster than current generation hardware.

Providing SLO Compliance on NVMe SSDs Through Parallelism Reservation

Non-Volatile Memory Express (NVMe) is a specification for next-generation solid-state disks (SSDs). Benefited from the massive internal parallelism and the high-speed PCIe bus, NVMe SSDs achieve extremely high data transfer rates, and they are an ideal solution of shared storage in virtualization environments. Providing virtual machines with Service Level Objective (SLO) compliance on NVMe SSDs is a challenging task, because garbage collection activities inside of NVMe SSDs globally affect the I/O performance of all virtual machines. In this study, we introduce a novel approach, called parallelism reservation, which is inspired by the rich internal parallelism of NVMe SSDs. The degree of parallelism stands for how many flash chips are concurrently active. Our basic idea is to reserve sufficient degrees of parallelism for read, write, and garbage collection operations, making sure that an NVMe SSD delivers stable read and write throughput and reclaims free space at a constant rate. The stable read and write throughput are proportionally distributed among virtual machines for SLO compliance. Our experimental results show that our parallelism reservation approach delivered satisfiable throughput and highly predictable response to virtual machines.

PCI Express-Based NVMe Solid State Disk

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.