Nonlinear Parasitic Capacitance Research Articles

Full ZVS Achievement for DCM Grid-Tied Inverter With Improved Average Current Model and Considering Nonlinear Parasitic Capacitance

Full ZVS Achievement for DCM Grid-Tied Inverter With Improved Average Current Model and Considering Nonlinear Parasitic Capacitance

Correction: Estimation of switching losses considering non-linear parasitic capacitances of GaN E-HEMT

Correction: Estimation of switching losses considering non-linear parasitic capacitances of GaN E-HEMT

Estimation of switching losses considering non-linear parasitic capacitances of GaN E-HEMT

Estimation of switching losses considering non-linear parasitic capacitances of GaN E-HEMT

An Accurate Analytical Model of SiC MOSFETs for Switching Speed and Switching Loss Calculation in High-Voltage Pulsed Power Supplies

Nanosecond output pulse and high efficiency are achieved in high-voltage pulsed power supplies (HVPPSs) by applying silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s), whose switching speed and switching loss are two vital characteristic parameters. However, the existing research on switching characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s is mainly based on the double pulse test circuits with inductive loads, which is not suitable for assessing the devices in HVPPSs with resistive loads. Besides, some simplified analytical methods in HVPPSs lead to poor precision. To accurately predict the switching behavior of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s in HVPPSs for guiding the design of gate driving circuits and power loops, this article proposes an accurate analytical model considering parasitic inductances, nonlinear parasitic capacitances, transfer characteristic, and output characteristics of SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. High-precision fitting of transfer characteristic is realized by using the Gaussian function. Besides, the dynamic parasitic gate-drain capacitance is measured by experiment, and three-dimensional curve fitting is performed on the output characteristics to exactly represent <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> -resistance. Furthermore, switching speed and switching loss can be directly calculated according to the solved state variables. Finally, the analytical model is verified by experiment, and the effects of gate driving circuits and power loops on switching characteristics are researched in detail.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

A 6-GHz Bandwidth Input Buffer Based on AC-Coupled Flipped Source Follower for 12-bit 8-GS/s ADC in 28-nm CMOS

This brief presents an input buffer based on AC-coupled flipped source follower (SF) for a 12-bit 8-GS/s time-interleaved (TI) ADC. The flipped SF can drive the ADC’s sampling capacitance with high linearity because the input MOS’s drain current is almost independent of the load capacitance. In addition, the inherent feedback reduces the input buffer’s output impedance, which improves the bandwidth when driving the complex wiring network of TI ADCs. The proposed AC-coupling structure enlarges the input signal range of the flipped SF extensively, making it practical to be used for high-speed ADCs. A compensation capacitor is used to compensate for the nonlinear parasitic capacitance of the input MOS to further improve the linearity. An 8-channel 12-bit 8GS/s TI ADC prototype with the proposed input buffer is implemented in a 28-nm mixed-signal CMOS process. Measured results show that the input bandwidth of the input buffer exceeds 6 GHz with 137-mW power supply. The ADC achieves SFDR of 68 dBFS and SNDR of 54.9 dB with 3.9-GHz, −1-dBFS input signal under 8-GS/s sampling rate. The total power consumption of the ADC is 1.05 W.

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC

This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.

Analysis and Design of Class E Frequency Multiplier With Shunt Linear and Nonlinear Capacitances at Any Duty Cycle

The theoretical efficiency of the class E frequency multiplier with arbitrary output frequency can reach 100% by controlling the phase of the output current to satisfy the ZVS/ZVDS condition. It is necessary to select the appropriate value of the shunt capacitance of the frequency multiplier for satisfying these two conditions. In general, the shunt capacitance of the transistor consists of the linear external capacitance and the nonlinear parasitic capacitance. Therefore, the conventional design method of treating shunt capacitance as purely linear is not accurate enough. In this brief, a class E frequency multiplier with shunt linear and nonlinear capacitances at any duty cycle is analyzed and designed, and the design curve is given in detail. The simulation and experimental results show high agreement with the theoretical analysis result.

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

An 8-bit 10-GHz 8 × time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.

Fast and simple model generation for superjunction power MOSFETs

This paper describes a new way to create a behavioral model for power MOSFETs with highly nonlinear parasitic capacitances like those based on superjunction (SJ) principles. The process ranges from a simple measurement to the final model for SPICE simulations. One of the benefits of the proposed modeling technique is that it does not require any information about the voltage-dependent capacitances of the MOSFET from the data sheet but instead relies on a simple measurement method using a vector network analyzer. The measurement data can be used for modeling all parasitic capacitances and inductances in the SPICE model. Compared to existing simulation models by the manufacturer, the proposed model promises better convergence, more accurate high-frequency behavior and faster simulation time. The advantages and disadvantages of this modeling technique are discussed.

Design of class‐E M amplifier with consideration of parasitic non‐linear capacitances and on‐state resistance

In this study, the design of the class-E M­ power amplifier is presented. In this design, the effects of on-state resistance and non-linear parasitic capacitances of the transistors are investigated. Two metal oxide semiconductor field-effect transistors (MOSFETs) of IRFZ24N and IRF510 with different drain-source resistances are used in the presented circuits. In the given design, the values of the operational frequency and duty ratio are 3.5 MHz and 0.5, respectively. This study shows the importance of considering non-linear parasitic elements of MOSFET, especially drain-source resistance in the designing of the class-E M power amplifiers. It is shown that the class-E M power amplifier with high MOSFET drain-source resistance needs high DC input voltage for both the primary and auxiliary circuits. In the previous works, non-linear on-state resistance and non-linear drain-source and gate-drain capacitances have not been included at the same time in the analyses. Two class-E M amplifiers contain IRF510 and IRFZ24N are designed, simulated, and measured. The efficiency equal to 96.6% with 11.851 W output power at 3.5 MHz and the efficiency equal to 88.4% with 12.361 W output power are achieved for presented class-E M amplifiers contain IRFZ24N and IRF510, respectively.

Switched-Capacitor Boost-Buck Ladder Converters With Extended Voltage Range in Standard CMOS

This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8-3.3-V, 0.18-$\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> output power density, and good correlation between measured and predicted results.

Analysis and Improvement of Capacitance Effects in 360–800 Hz Variable On-Time Controlled CRM Boost PFC Converters

In critical conduction mode (CRM) boost power factor correction (PFC) converters, the input filter capacitor (IFC) is used to limit the propagation of switching noise into the ac line and the inherently existing parasitic capacitance of power semiconductor devices resonates with the boost inductor to achieve soft switching, which is voltage dependent and nonlinear. However, IFC leads to the crossover distortion of the rectified input voltage and thus the zero-crossing distortion of input current, which is ignored at the utility line frequency (50-60 Hz) since the effect of IFC is relatively small in this case. However, for wide variable frequency (360-800 Hz) power system, the effect of IFC becomes severe and unnegligible, which causes the deterioration of input current total harmonics distortion (THD). Besides, the nonlinearity of the parasitic capacitance is ignored and an equivalent constant linear capacitance is used in existing variable on-time (VOT) controls, which will cause the inaccuracy of VOT control, and thus, exacerbates the input current distortion. In order to improve the input current THD at high line frequency, this article proposes the IFC compensation method to minimize the effect of IFC and a variable parameter control is also achieved to suppress the effect of nonlinear parasitic capacitance. The experimental results of an 115-Vac-input 160-W/270-Vdc-output CRM boost PFC prototype are presented to verify the effectiveness and advantages of the proposed VOT methods. With the proposed methods, the input current THD is only 2.04% at 360 Hz input with full load and 3.14% at 800 Hz input with full load.

High-Switching-Frequency TCM Digital Control for Bidirectional-Interleaved Buck Converters Without Phase Error for Battery Charging

This article proposes a high-performance, high-switching-frequency triangular-conduction-mode (TCM) bidirectional-interleaved buck converter for battery charging using digital control. Accurate conditions for achieving zero-voltage switching (ZVS) without zero-crossing detection (ZCD) are derived while considering the nonlinear parasitic capacitance of the switch components. This article also optimizes the method of calculating the switching frequency to reduce the delay time of pulsewidth modulation, thereby enhancing system stability. The conventional control method has inadequate resolution in the phase shift register of the digital controller under high switching frequency, hindering perfect interleaving of the two phases at 180°, which affects the characteristics of current ripple offset. The proposed control method effectively reduces the phase error between the two phases in an interleaving structure under high-frequency operation. In this way, full-range ZVS can be achieved when the circuit operates at the correct switching frequency. ANSYS Q3D Extractor software is employed to simulate the impedances of the power loops and investigate parasitic parameters, enabling optimization of the layout and modification of the switching frequency. An experimental prototype of a bidirectional buck converter using GaN switches was implemented with an output power of 1 kW, an input voltage of 66 V, an output voltage of 35-50 V, a switching frequency of 350 kHz-1 MHz, a highest efficiency of 97.52%, and a power density of 10 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS

This paper presents a highly linear BiCMOS sample and hold amplifier (SHA) providing 2.8-GS/s intermediate frequency (IF) sampling for a 1-GHz input bandwidth spanning from 1.5 to 2.5 GHz. A single-transistor hold-mode feedthrough cancellation technique is implemented to remove distortion resulting from the nonlinear parasitic capacitance at the sampling node. The SHA is designed in a mainstream 130-nm BiCMOS technology using SiGe heterojunction bipolar transistors to buffer and sample the wideband input. The proposed SHA enables monolithic integration with a high-speed analog-to-digital converter core to realize a high-performance converter solution. This independent sampling front end occupies a core chip area of 0.6 mm2 and consumes an average power of 1.26 W. The SHA is a pseudo-differential open-loop design that includes two cascaded track-and-hold amplifiers, a high-speed clock driver, and externally adjustable current mirror biases. The high-speed clock drivers and buffers add 170 mW to the total power consumption. The measurements of the fabricated SHA show a 10-bit effective resolution across the 1-GHz IF bandwidth and < −61-dBc HD2 and HD3.

Improved SiC Power MOSFET Model Considering Nonlinear Junction Capacitances

Silicon carbide (SiC) power metal–oxide–semiconductor field-effect transistors (mosfet s) have been applied in high-power and high-frequency converters recently. To effectively predict characteristics of SiC power mosfet s in the design phase, a simple and valid model is needed. In this paper, a simple improved SiC power mosfet behavioral model is proposed using SPICE language. Key parameters in the model are analyzed and determined in detail, including parasitic parameters of the power module, steady-state characteristic parameters, and nonlinear parasitic capacitances. The effect of negative turn- off gate drive voltage is considered and a continuously differentiable function is proposed to describe the gate–source capacitance. Experimental validation is performed under a double pulse circuit employing an N -channel power mosfet half-bridge module CAS300M12BM2 (Cree Inc.) rated at 300 A/1200 V. The main switching dynamic characteristic parameters of the model have been compared with those of the measured results. The results show that taking gate–source capacitance as a linear value as most previous models do will cause significant turn- on deviations between experiment and simulation results, while the improved model is more accurate compared with the measured results.

Closed-Form Solution for Efficient ZVS Modulation of DAB Converters

A directly employable closed-form analytical solution for the calculation of an efficient, full-operating-range zero voltage switching (ZVS) modulation scheme for bidirectional dual active bridge (DAB) dc–dc converters is presented. Contrary to the analytical ZVS modulation schemes previously proposed in literature, the amount of charge that is required to charge the nonlinear parasitic output capacitances of the switches during commutation is incorporated, ensuring complete commutation of the bridge legs and ZVS of the switching devices. Besides quasi-lossless ZVS, the resulting modulation scheme leads to near-minimum high-frequency circulating currents and thus, minimum conduction losses under the condition of ZVS and for given values of the inductances and transformer turns ratio. Although modifiable for other implementations, the method is demonstrated for a full-bridge full-bridge DAB as a core part of a single-phase, single-stage, bidirectional, isolated ac–dc converter. The resulting modulation scheme is compared with a ZVS modulation scheme calculated using a previously published numerical approach, proving its effectiveness. Experimental results obtained from a state-of-the-art, $\text{3.7}\; \text{kW}$ converter prototype which interfaces a $\text{400}\; \text{V}$ battery with the $\text{230}\;\text{V}$ , $\text{50}\;\text{Hz}$ utility grid are given to validate the theoretical analysis and practical feasibility of the proposed strategy.

Design, analysis and implementation of class-E ZCS/ZCDS power amplifier for any duty ratio with nonlinear output parasitic capacitance

This paper gives the design and analysis approaches for the class-E power amplifier with a shunt inductor under the nominal conditions, i.e., zero-current switching (ZCS) and zero-current derivative switching (ZCDS), with taking into account the MOSFET nonlinear output parasitic capacitance at any duty ratio. Although, the class-E ZCS/ZCDS conditions obtained high-efficiency, but the switch-current waveform affected by the slope of the voltage across the MOSFET nonlinear drain-to-source parasitic capacitance during the switch-off state, which restricted the operating frequency. On the other hand, the duty ratio is an adjustment parameter to obtain high-frequency operation. Therefore, the duty ratio and the MOSFET nonlinear output parasitic capacitance are required to satisfy the class-E ZCS/ZCDS conditions. The verification of the proposed analysis expressions is performed by fabricating of the class-E power amplifier with the output power 13.2-W at the operating frequency 4-MHz, and the laboratory experiments are performed, which achieved 90.9 % power conversion efficiency. The validity of proposed analytical expressions had been proved by the achieved good agreement between waveforms obtained from the PSpice-simulations and circuit laboratory experiments, which satisfied both ZCS and ZCDS conditions.

Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches. However, the power switches are conventionally characterized in terms of switching time and/or gate charge with little insight into the nonlinearities of the parasitic capacitances. This paper proposes a modeling method that can be utilized to systematically analyze the nonlinear parasitic capacitances. The existing ways of characterizing the off-state capacitance can be extended by the proposed circuit model that covers all the related states: off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize the nonlinearities of the parasitic capacitances. The equivalent circuits in different states and the evaluation equations are provided.DOI: http://dx.doi.org/10.5755/j01.eie.22.3.15312

Optimal ZVS Modulation of Single-Phase Single-Stage Bidirectional DAB AC–DC Converters

A comprehensive procedure for the derivation of optimal, full-operating-range zero voltage switching (ZVS) modulation schemes for single-phase, single-stage, bidirectional and isolated dual active bridge (DAB) ac-dc converters is presented. The converter topology consists of a DAB dc-dc converter, receiving a rectified ac line voltage via a synchronous rectifier. The DAB comprises primary and secondary side full bridges, linked by a high-frequency isolation transformer and a series inductor. ZVS modulation schemes previously proposed in the literature are either based on current-based or energy-based ZVS analyses. The procedure outlined in this paper for the calculation of optimal DAB modulation schemes (i.e., combined phase-shift, duty-cycle, and switching frequency modulation) relies on a novel, more accurate, current-dependent charge-based ZVS analysis, taking into account the amount of charge that is required to charge the nonlinear parasitic output capacitances of the switches during commutation. Thereby, the concept of “commutation inductance(s)” is shown to be an essential element in achieving full-operating-range ZVS. The proposed methods are applied to a 3.7 kW, bidirectional, and unity power factor electric vehicle battery charger which interfaces a 400 V dc-bus with the 230 Vac, 50-Hz utility grid. Experimental results obtained from a high-power-density, high-efficiency converter prototype are given to validate the theoretical analysis and practical feasibility of the proposed strategy.