Noise Transfer Function Research Articles

Compositional and entropy indirect noise generated in subsonic non-isentropic nozzles

Abstract

Compensating Processing Delay in Excess of One Clock Cycle in Noise Shaping Loops Without Altering the Filter Topology

This work presents an analytical method to design a stable loop filter for a noise shaper with parasitic delays or poles in the loop. This method does not require an increase in the order of the loop or extra feedback paths and keeps the original poles and zeros of the noise-transfer function at the same location. The method has been applied to a low-pass loop filter with a parasitic unit delay and a band-pass loop filter with either three unit delays or a high-frequency pole, obtaining stable loop filters in all three cases.

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC's speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.

A distributed interpolative sigma-delta interface for fluxgate sensor

This paper presents a sigma-delta interface for fluxgate sensor based on a single-loop high-order modulation. A feedforward summation loop structure can reduce the linearity overload in integrators and the swing of integration signals. A Local feedback branch is proposed to realize the zero of noise transfer function (NTF) optimization and enhance noise shaping performance within signal band. The interface is fabricated in a standard 0.5 [Formula: see text]m CMOS process and the active circuit area is about 13 mm2. The chip consumes 120 mW from a 10 V supply with a sampling clock of 250 k Hz. The average noise floor of the digital fluxgate is about −115 dBV/Hz[Formula: see text] over a 100 Hz bandwidth.

Importance of Vehicle Body Elements and Rear Axle Elements for Describing Road Booming Noise

For investigating influences of vehicle components on the acoustic comfort at low frequencies, e.g., the booming noise behavior of a vehicle, building a whole car simulation model is useful. To reduce the model’s complexity and to save resources in the validation process, we first identify relevant components before building the model. Based on previous studies, we focus on the vehicle’s body and the rear axle. In this paper, we analyze which axle and body elements are crucial for describing road booming noise. For this purpose, we use impact measurements to examine noise transfer functions of the body and a vibro-acoustical modal analysis to identify coupled modes between the body’s structure and the interior cavity. For investigating relevant force paths from the rear axle to the body, we used a chassis test bench. We identify the main transmission paths of road booming noise and highlight which axle and body components have an influence on them. Mainly the rear axle in its upright direction in combination with a rigid body movement of the rear tailgate coupled with the first longitudinal mode of the airborne cavity causes road booming noise. Furthermore, the rear axle steering, the active roll stabilization and the trim elements of the vehicle’s body are essential to describe road booming noise. The results can be used to set priorities in the validation of individual axle and body components for future simulation models. We found that the ventilation openings, the front seats, the headliner, and the cockpit of a vehicle have little influence on its noise transfer functions from the rear axle connection points to the driver’s ear between 20 and 60 Hz.

A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes $59.9~\mu \text{W}$ of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

8fJ/Step Bandpass ADC With Digitally Assisted NTF Re-Configuration

In this work we propose a single channel band-pass (BP) SAR ADC with dynamic noise transfer function (NTF) re-configuration. The proposed ADC employs a low-power two-stage architecture. After the SAR finishes quantization, the residue is extracted by firing the comparator multiple times. An estimate of the residue is obtained by employing a maximum likelihood based estimator (MLE). The output of the ADC is obtained by subtracting a delayed version of the estimated residue from the SAR output thus generating a complex NTF with multiple notches in the spectrum. A 65nm ADC prototype achieves 74.1/78dB SNDR/DR over a 101.2kHz bandwidth while consuming $17~\mu \text{W}$ from a 1V supply at 2.43MS/s. The ADC core occupies an area of 0.12mm2. The ADC achieves 8fJ/c-step bandpass FoM which is $85\times $ better than state-of-the-art BP ADCs with similar bandwidth and $8.7\times $ better than all reported state-of-the-art BP ADCs.

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta–Sigma Modulator

We combine a first-order single-bit CTΔΣM employing finite impulse-response (FIR) feedback with a 1-bit second-order ΔΣ back end to achieve a modulator with maximum stable amplitude (MSA) that is close to full scale, and a third-order overall noise transfer function (NTF). FIR feedback is used in the input stage to reduce clock-jitter sensitivity, improve linearity, and reduce chopping artifacts. We show that in a MASH ADC, FIR feedback has the additional benefit of filtering the error waveform of the first stage that is fed into the second stage. We apply the principle to an audio continuous-time delta-sigma modulator. A prototype chip, fabricated in 180-nm CMOS to demonstrate the principle, achieves 100.9-dB SNDR in a 24-kHz bandwidth and dissipates 265μW. The resulting Schreier figure of merit is 180.5 dB.

A second-order noise-shaping SAR ADC with error-feedback structure and data weighted averaging

This paper presents a second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) employing the error-feedback (EF) structure. With the finite impulse response (FIR) filter based on a single operational transconductance amplifier (OTA), it realizes noise transfer function (NTF) zeros optimization. The specifications of OTA are relaxed without high-gain and fast-settling. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-coded 4-bit MSBs are implemented with the data weighted averaging (DWA) technique. The overall architecture is simple and robust. It does not need additional complicated digital calibrations, and only requires minor modifications to the standard SAR ADC. Design and simulation in a 130 ​nm CMOS process, the prototype consumes 96 ​μW of power when operating at 1 ​MS/s sampling frequency. The proposed ADC achieves peak Schreier FoM of 165 ​dB with 76.95 ​dB signal to noise and distortion ratio (SNDR) and 97.34 ​dB spurious free dynamic range (SFDR) at an oversampling ratio (OSR) of 8.

Noise Analysis of a Passive Resonant Laser Gyroscope.

Large-scale laser gyroscopes have found important applications in Earth sciences due to their self-sufficient property of measurement of the Earth’s rotation without any external references. In order to extend the relative rotation measurement accuracy to a better level so that it can be used for the determination of the Earth orientation parameters (EOP), we investigate the limitations in a passive resonant laser gyroscope (PRG) developed at Huazhong University of Science and Technology (HUST) to pave the way for future development. We identify the noise sources from the derived noise transfer function of the PRG. In the frequency range below , the contribution of free-spectral-range (FSR) variation is the dominant limitation, which comes from the drift of the ring cavity length. In the to frequency range, the limitation is due to the noises of the frequency discrimination system, which mainly comes from the residual amplitude modulation (RAM) in the frequency range below 2 Hz. In addition, the noise contributed by the Mach–Zehnder-type beam combiner is also noticeable in the 0.01 to 2 Hz frequency range. Finally, possible schemes for future improvement are also discussed.

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier. The proposed closed-loop dynamic amplifier combines the merits of closed-loop architecture and dynamic operation, realizing robustness, high accuracy, and high energy-efficiency simultaneously. It is embedded in the loop filter of an NS SAR design, enabling the first fully dynamic NS-SAR ADC that realizes sharp noise transfer function (NTF) while not requiring any gain calibration. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 83.8 dB over a bandwidth of 625 kHz while consuming only $107~\mu \text{W}$ . It results in an SNDR-based Schreier figure-of-merit (FoM) of 181.5 dB.

Noise-Coupled Time-Interleaved Delta–Sigma Modulator with Reduced Hardware Complexity

Developing an analog-to-digital converter (ADC) based on the time-interleaved delta–sigma modulator (TIDSM) is an appropriate technique to attain high-speed ADCs. TIDSMs can be successfully accomplished with the aid of developing the block digital filtering (BDF) method. In this approach, [Formula: see text] mutually cross-connection delta–sigma modulators are used, whereby each one of them operates at a sampling rate of [Formula: see text], leading to an effective sampling rate of [Formula: see text]. In this study, a novel structure is proposed based on the Noise Coupled time-interleaved delta–sigma modulator (NC-TIDSM) with reduced hardware complexity. This structure not only increases the overall noise transfer function (NTF) order, but also reduces the hardware element counts. The simulation results demonstrate that the SNDRs of the first-order two-channel and four-channel NC-TIDSM with reduced hardware are 13 and 15 dB better than those of their BDF technique counterparts; also, the SNDR of the second-order two-channel NC-TIDSM with reduced hardware is 8 dB better than that of their BDF technique counterpart; also, the hardware element quantities are reduced dramatically. Moreover, some practical challenges such as the finite op-amp’s gain and mismatching effects that directly affect the circuit implementation of the proposed structure have been described. Furthermore, the hardware complexity of the proposed structures is reduced considerably in comparison to that of the BDF technique with the NC-TIDSM structure.

Reconfigurable Digital Delta-Sigma Modulation Transmitter Architecture for Concurrent Multi-Band Transmission

This paper presents a reconfigurable delta-sigma modulation (DSM) architecture for concurrent multi-band transmission. The reconfigurability in terms of carrier spacing and the number of simultaneous carrier transmission is useful for applications such as carrier aggregation in 5G. This paper uses $4^{th}$ order reconfigurable multi-band DSM (RMB-DSM) such that the zeros of the noise transfer function can be reconfigured to fall at multiple frequencies, where the carriers are being aggregated. The quantization noise between the transmission bands is a critical issue in the case of multi-band transmission. Therefore, a multi-band additional noise shaping (ANS) function is also introduced, which generates notches around each carrier and reduces the noise level between the multiple pass-bands. The proposed scheme has been validated in simulation, as well as in experiment for aggregating up to four 15 MHz long term evolution (LTE) signals with an overall aggregated bandwidth of 60 MHz. Measurement results show a 10-25% improvement in coding efficiency and 15-35 dB improvement in noise level near the operating frequency band using the proposed multi-band augmented noise shaping technique, as compared to the standard DSM. The corresponding improvement of 8% in the overall efficiency is observed by using the proposed multi-band augmented noise shaping technique.

An Optimization Framework for the Design of Noise Shaping Loop Filters with Improved Stability Properties

A framework using semidefinite programming is proposed to enable the design of sigma delta modulator loop filters at the transfer function level. Both continuous-time and discrete-time, low-pass and band-pass designs are supported. For performance, we use the recently popularized Generalized Kalman–Yakubovic–Popov (GKYP) lemma to place constraints on the $$\mathcal {H}_\infty $$ norm of the noise transfer function (NTF) in the frequency band of interest. We expand the approach to incorporate common stability criteria in the form of $$\mathcal {H}_2$$ and $$\ell _1$$ norm NTF constraints. Furthering the discussion of stability, we introduce techniques from control systems to improve the robustness of the feedback system over a range of quantizer gains. The performance-stability trade-off is examined using this framework and motivated by simulation results.

Numerical Noise Transfer Analysis of a Flexible Supported Gearbox Based on Impedance Model and Noise Transfer Function

To investigate the gearbox radiation noise properties under various rotational speeds, a noise prediction method based on impedance model and noise transfer function (NTF) is proposed. One only needs to extract the NTF of the housing once rapid gearbox noise prediction under different working conditions is realized. Taking a flexible supported gearbox as a research object, the external excitation of the housing (the bearing excitation load and isolator excitation load) is calculated through a gear-housing-foundation-coupled impedance model, and the noise transfer function is simulated through the vibroacoustic-coupled boundary element model; then the radiation noise is obtained. Based on this model, the noise transfer analysis of the housing is carried out, different excitation components and NTF components are compared, and the contributions of different excitation components to noise are compared. Results show that the radiation noise of gearbox is mainly excited by the high-speed bearing, while the low-speed bearing and isolator have little influence on noise. At low speed, vertical force, axial force, and moment excitation of bearings all contribute to the radiation noise while at high speed, the gearbox radiation noise is mainly generated by vertical excitation force of bearings.

Performance Evaluation of Incremental Sigma-Delta ADCs Based on their NTF

In this brief the performance of I-SD ADCs based on the spectral description is discussed. It is based on the modulator and the reconstruction filter and accounts for the applied reset. The definition of the overall noise transfer function (NTF) enables the analysis of the performance of I-SD ADCs in frequency domain and consequently makes it possible to explain the inherent behavior of this type of ADC including reconstruction filter and non-idealities. In the state of the art, the performance of an I-SD ADC is either obtained by simulations or predicted via time-domain considerations. However, these simulations can become time consuming and time-domain considerations neglect non-idealities, especially in the case of a CT modulator. Only recently, a general way to describe the NTF of DT and CT I-SD ADCs was introduced. This brief gives a detailed analysis of the NTF of I-SD ADCs and the impact of its properties on the resulting SQNR. It discusses the influence of common reconstruction filters and based on this analysis, it introduces as an example a modified CoI filter that allows to improve the ADC's performance.

Intensity noise as a driver for transverse mode instability in fiber amplifiers

The effect of transverse mode instability (TMI) is currently the main limitation for the further average-power scaling of fiber laser systems with diffraction-limited beam quality. In this work a main driving force for TMI in fiber amplifiers is identified. Our experiments and simulations illustrate that the performance of fiber laser systems in terms of their diffraction-limited output power can be significantly reduced when the pump or seed radiation exhibit intensity noise. This finding emphasizes the fact that the TMI threshold is not only determined by the active fiber but, rather, by the whole system. In the experiment an artificially applied pump intensity-noise of 2.9% led to a reduction of the TMI threshold of 63%, whereas a similar seed intensity-noise decreased it by just 13%. Thus, even though both noise sources have an impact on the TMI threshold, the pump intensity-noise can be considered as the main driver for TMI in saturated fiber amplifiers. Additionally, the work unveils that the physical origin of this behavior is linked to the noise transfer function in saturated fiber amplifiers. With the gained knowledge and the experimental and theoretical results, it can be concluded that a suppression of pump-noise frequencies below 20 kHz could strongly increase the TMI threshold in high-power fiber laser systems.

A Dividerless Ring Oscillator PLL With 250fs Integrated Jitter Using Sampled Lowpass Filter

This brief presents a novel ring oscillator based phase lock loop architecture that is capable of wideband, dividerless integer-N synthesis. The noise transfer function of the presented architecture is the same as a sub-sampling phase lock loop (PLL). Like a sub-sampling PLL, the presented architecture removes the phase detector and charge pump’s $N^{2}$ noise that dominates the in-band noise of traditional PLLs. This noise reduction allows the presented ring oscillator PLL to operate with integrated jitter as low as 250fs. Unlike sub-sampling PLLs, the presented architecture moves the sampling block downstream of the loop filter. As the sampled data is lowpass filtered, only low frequency sampling blocks are required, which removes the power and area overheads associated with directly sampling the voltage controlled oscillator. Measurement results show the presented PLL is capable of locking over a wide range of 1.2-2.5GHz. The presented PLL is fabricated in 65nm bulk CMOS, and demonstrates a figure of merit of −242.7dB, which is among best in class for ring oscillator PLLs. Furthermore, an area of 0.0066 mm2 is consumed, which represents the smallest published sub-sampling ring oscillator PLLs.

A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL

This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage, which are suitable for MDLLs. This can reduce the output jitter and power consumption of the proposed structure. An improved frequency multiplication is used to multiply the generated frequencies, which reduces the occupied area and power consumption in comparison to conventional ECDLL. Since the phase-noise of VCDL is affected by the noise of control voltage, the noise transfer functions of control voltage will be transferred to the ECDLL output. Reducing noise from the delay cell can help reduce the overall system phase noise. Post-layout simulations with TSMC 0.13 μm technology are performed using CMOS technology in the frequency range of 8 MHz to 1 GHz, and the RMS jitter is 1.06 ps at a frequency of 1 GHz. Reduction in the number of delay cells and use of low-power 50% duty cycle corrector can cause low output jitter and reduce power consumption. The overall power consumption of the system is 3.01 mW at a frequency of 1 GHz in the fast-locking situation with 1.2 V power supply, which demonstrates improvement in the results compared to previous related works.

Efficient Jitter Analysis for a Chain of CMOS Inverters

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.