Measured Noise Figure Research Articles

A 245 GHz LNA in SiGe Technology

A five-stage differential SiGe low noise amplifier (LNA) in cascode topology is presented. Transformer coupling is used between the stages to obtain inter-stage matching. The single ended input and output of the LNA are realized by baluns. The LNA has 18 dB of gain at 245 GHz and a 3 dB bandwidth of 8 GHz. A noise figure of 11 ±1 dB NF of the LNA at 245 GHz was measured by the Y-factor method. These values represent the highest gain and the lowest measured noise figure at 245 GHz reported for a SiGe LNA so far. The LNA draws 82 mA at a supply voltage of 3.7 V.

A Highly Reconfigurable Low-Power CMOS Directional Coupler

This paper presents a highly reconfigurable, low-power, and compact directional coupler. The coupler uses varactors and novel active inductors to achieve wide tuning ranges of operating frequencies and coupling coefficients. The use of a low-pass circuit architecture with only two inductors minimizes chip area, power consumption, and noise. The coupler is implemented in a 0.13-μm CMOS process. It occupies an area of 350 μm× 340 μm and consumes 40 mW or less power. The obtained 1-dB compression point is -3.2 dBm, and the measured noise figure is ~ 23 dB. These parameters compare favorably with previously published reconfigurable couplers. The measured coupling coefficient can be tuned from 1.3 to 9.0 dB at 4 GHz with 32 dB or better isolation and 15 dB or better return loss. The operating center frequency can be tuned from 2.0 to 6.0 GHz for a nominal 3-dB operation. These results agree with theoretical predictions and simulations reasonably well.

Dual cross-coupling LNA with forward body bias technique

A fully integrated low-power LNA with dual cross-coupling and forward body bias (FBB) techniques is presented. The first cross-coupling circuit is applied at the transconductance stage. By connecting body nodes to each other's source terminals, the body cross-coupling network forms the gate-driven and body-driven simultaneously input stage to gain its effective transconductance, which in turn improves the noise performance and decreases current consumption. In addition, the second capacitor cross-coupling configuration is applied at the input stage to form a feed-forward connection, which results in not only boosting the effective transconductance, but also reducing the influence of the gate noise from the input transistors as well. Moreover, to decrease the overall power consumption further, the FBB technique is employed to lower the supply voltage. The measured noise figure is lower than 3.38 dB and the core circuit consumes only 2.16 mW.

340 GHz Integrated Receiver in 250 nm InP DHBT Technology

A 340 GHz integrated receiver based on a 250 nm InP DHBT technology is presented in this paper. It consists of a 2 × 2 differential patch array antenna, a sub-harmonically pumped Gilbert mixer and an IF buffer amplifier. Performance of the integrated receiver is evaluated by setting up a RF link in the frequency band of 302-338 GHz. At 338 GHz RF and 170 GHz LO, the peak conversion gain of 11.8 and 14.0 dB is achieved with and without antenna, respectively. A double-sideband noise figure of 17 dB at room temperature is obtained from direct noise figure measurement .

A D-Band Cascode Amplifier With 24.3 dB Gain and 7.7 dBm Output Power in 0.13 $\mu$m SiGe BiCMOS Technology

This letter describes a D-band 3-stage cascode amplifier developed using the IHP 0.13 μm SiGe BiCMOS technology. The amplifier is implemented with low-loss transformer for inter-stage matching and single-to-differential transformation. The large-signal characteristics of the cascode HBT configuration are used to optimize the bias condition for highest output power and gain performance. A measured amplifier achieves a peak power gain of 24.3 dB, with a 3 dB bandwidth of 20 GHz centered at 130 GHz. The amplifier exhibits a saturated output power of 7.7 dBm and an output 1 dB gain compression point of 6 dBm with a power consumption of 84 mW. The measured noise figure is 6.8 dB at 130 GHz and stays under 8 dB over the 3 dB bandwidth. To the best of our knowledge, the proposed amplifier exhibits the highest gain and output power among the silicon-based D-band amplifiers reported so far.

Third order integrable UHF bandpass filter using active inductors

AbstractIn this article, an UHF third order bandpass filter based on an high‐Q active inductor (AI) is described and measurement results, performed on a prototype board, are presented and compared with software simulations. The designed AI includes a passive variable phase‐ and amplitude‐compensating network and a highly linear inverting amplifier, forming a gyrator‐C architecture that gives to the filter also frequency and amplitude tuneability proprieties. The fabricated Butterworth filter has a center frequency of 600 MHz and a measured noise figure of 11 dB with a 5 dBm 1‐dB compression point and a 82 dB dynamic range. All passive components values have been chosen to allow the circuit to be completely integrated in a standard IC design. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1426–1429, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26857

Analysis and Design of a 60 GHz Wideband Voltage-Voltage Transformer Feedback LNA

To cope with the problem of instability and imperfect reverse isolation, a millimeter-wave voltage-voltage transformer feedback low noise amplifier has been analyzed, designed, and measured in CMOS 65 nm technology. Analytical formulae are derived for describing the stability, gain, and noise in this circuit topology. An analogy with the classic concept of Masons's invariant is used to illustrate how the transformer feedback provides the required reverse isolation in the LNA. Based on the developed theoretical analysis, the circuit is implemented as a fully integrated 60 GHz two-stage differential low noise amplifier in 65 nm CMOS technology. A flat gain of 10 dB is achieved over the entire 6 GHz bandwidth. The measured noise figure is 3.8 dB.

UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations

An integrated ultrahigh-frequency (UHF) receiver is presented. A systematic analysis to quantify the interdependence of baseband filter and analog-to-digital converter (ADC) dynamic range in broadband receivers is presented. This analysis shows that: (1) low-order Butterworth filters are favorable when undesired power is dominated by far out blockers and (2) high-order inverse Chebyshev filters can reduce the resolution of a subsequent ADC by up to two additional bits in the presence of adjacent analog narrowband blockers. Based on the analysis, a cascaded, programmable, hybrid active-RC and switched-capacitor (SC) baseband filter is proposed. An all-digital nonoverlap clock tuning system to minimize the variation of available settling time window in SC circuits is also proposed. The receiver integrates the proposed filter with an RF variable gain amplifier (RFVGA) and a passive mixer. This receiver achieves a measured noise figure of 7.9 dB, an IIP3 of -8 dBm at maximum gain and +2 dBm at 9-dB RF attenuation. The chip consumes 120 mW (RFVGA, mixer and I-channel baseband) from 1.8-V analog/2.5-V digital dual supply and occupies 2.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in IBM 0.18-μm RF CMOS technology.

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18 μm CMOS

This paper presents a wideband low noise amplifier (LNA) for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate-inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of −3 dB bandwidth and 16 dB of gain. The gain variation is within ±0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure (NF) and average IIP3 are 3.4 dB and −2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.

Noise figure measurement of three-port differential low-noise amplifiers

A measurement procedure to de-embed the noise figure (NF) of a three-port differential low-noise amplifier (LNA) from single-ended (SE) measurements is presented. An approximate solution for the differential NF is found in terms of two SE noise figure and gain measurements and the sensitivity of the de-embedded NF to unsymmetrical performance is analysed. The theory presented is applied to a three-port differential LNA and the de-embedded NF is compared to that of an equivalent SE LNA design.

A Subthreshold CMOS RF Front-End Design for Low-Power Band-III T-DMB/DAB Receivers

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-μm CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

Fully Integrated Switch-LNA Front-End IC Design in CMOS: A Systematic Approach for WLAN

A fully integrated front-end IC is demonstrated for 802.11b/g transceivers with integrated power amplifiers. The SP3T-LNA architecture integrates Bluetooth® functionality with transmit and receive for wireless LAN. The transmit switch achieves a P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> greater than 33.0 dBm at 2.5 GHz by employing a cross-biasing approach, transistor stacking and deep n-well process. Power handling techniques used for the switches and the associated performance tradeoffs are discussed. The measured noise figure of the LNA and the receive chain comprising both an LNA and a switch is 1.5 dB and 3.0 dB, respectively. The LNA achieves an IIP3 of 7.0 dBm while consuming 7.0 mA of current. The measured switching times are less than 350 ns. The front-end IC employs a 3.3 V supply and occupies 0.64 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 0.18 μm bulk CMOS technology.

A Tuneable Active Inductor With High Dynamic Range for Band-Pass Filter Applications

An approach for the design of high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> active inductor (AI) with high dynamic range is presented. The proposed AI includes a passive variable phase- and amplitude-compensating network and a highly linear inverting amplifier, forming a gyrator-C architecture. The equivalent inductance and resistance values are tunable in a wide frequency range; outside the operating frequency band, the inductor equivalent resistance increases, improving signal rejection for band-pass filter applications. As a feasibility demonstration, a first-order active band-pass filter using the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> active inductance has been fabricated and tested. The filter has a center frequency of 600 MHz and a measured noise figure of 11 dB with a 5-dBm 1-dB compression point and an 82-dB dynamic range.

A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 μm RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of −39 dBm. The measured phase noise is better than −105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.

Characterization of the Noise Parameters of SiGe HBTs in the 70–170-GHz Range

Noise parameter ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">opt</sub> , and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R n</i> ) measurements of SiGe HBTs are provided for the first time in the 70-170-GHz range. In the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> -band, this is accomplished by integrating on a single chip a source impedance tuner with the device-under-test and a low-noise amplifier with 3.8-dB noise figure. Noise-figure measurements were performed over multiple source impedances using a commercial single-sideband downconverter. In the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> -band, where off-chip setup losses are overwhelming, the source impedance tuner, the transistor under test, and the entire receiver with a noise figure of 10 dB were integrated on a single silicon die, and direct noise-figure measurements were conducted first on the test setup with the transistor under test, and next on the reference receiver without the test transistor. Both analog and digital source impedance tuners, based on n-MOSFET variable resistors, n-MOSFET switches, and accumulation-mode varactors, have been designed and characterized. Finally, the existing technique to extract the SiGe HBT noise parameters from <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</i> -parameter measurements, without any noise-figure measurements, is refined to include noise correlation and is validated up to 170 GHz. The measured source-pull and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Y</i> -parameters results show that the minimum noise figure of state-of-the-art SiGe HBTs remains below 5 dB throughout the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</i> -band.

A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications

This paper describes a fully integrated 130 nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9 GHz, and as well as 5.1-5.9 GHz bands covering whole frequency spectrum of fixed and mobile WiMAX and WLAN. The measured noise figure of the receiver is 3.6-4.2, 4.2-4.7, and 5.4-6.2 dB for each 2/3/5 GHz bands respectively. The measured PLL phase noise from 1 kHz to 10 MHz is 0.5/0.8/0.95 rms degree for 2/3/5 GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to linear RX and TX signal paths and low integrated PLL phase noise characteristics.

Determining Noise Temperature of a Noise Source Using Calibrated Noise Sources and an RF Attenuator

A system to measure the noise temperature (NT) of noise sources is implemented in the frequency range of 18-26.5 GHz for the case where noise sources commercially available have only one nominal NT, e.g., 9500 K being equivalent to 15-dB excess noise ratio. For the Y-factor method, two noise sources, i.e., a noise source and another with a radio-frequency attenuator, serve as the standard noise sources. The noise power output of the noise sources are measured using a commercial noise figure measurement instrument. Measurement results are presented, and its uncertainty has been evaluated to be 0.23-0.25 dB (k = 2) .

Direct parameter-extraction method for MOSFET noise model from microwave noise figure measurement

A new method for the determination of the four noise parameters of the metal oxide semiconductor field effect transistors (MOSFETs) based on the noise figure measurement system without microwave tuner is presented. The noise parameters are determined based on a set of analytical expressions of noise parameters by fitting the measured noise figure of the active device. These expressions are derived from an accurate small signal and noise equivalent circuit model, which takes into account the substrate parasitics, pad capacitances, and series inductances. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for 0.5 × 5 × 16 μm, 0.35 × 5 × 16 μm and 0.18 × 5 × 16 μm (gate length × number of gate fingers × unit gate width) MOSFETs.

CMOS Programmable Gain Distributed Amplifier With 0.5-dB Gain Steps

A new CMOS programmable gain distributed amplifier with 0.5-dB gain steps is fabricated in a 130-nm process. The circuit is designed to demonstrate broadband (>1 decade) programmable gains with excellent matching and high isolation for use in RF integrated-circuit testing. The measured slope of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> loss is approximately 3 dB/decade over frequencies from 0.8 to 9 GHz where input and output return losses are better than roughly 10 dB; the measured input 1-dB compression point and third-order intermodulation intercept point at 2.78 GHz for the maximum 2.5-dB gain is 1 and 12.5 dBm, respectively. The measured noise figure is below 9.5 dB at 9 GHz. The circuit consumes approximately 40 mW total from 3.1-V analog and 1.5-V digital supplies.

Fully integrated 60 GHz transceiver in SiGe BiCMOS, RF modules, and 3.6 Gbit/s OFDM data transmission

A fully integrated transmitter (TX) and receiver (RX) front-end chipset, produced in 0.25 µm SiGe:C bipolar and complementary metal oxide semiconductor (BiCMOS) technology, is presented. The front-end is intended for high-speed wireless communication in the unlicensed ISM band of 9 GHz around 60 GHz. The TXand RX features a modified heterodyne topology with a sliding intermediate frequency. The TX features a 12 GHz in-phase and quadrature (I/Q) mixer, an intermediate frequency (IF) amplifier, a phase-locked loop, a 60 GHz mixer, an image-rejection filter, and a power amplifier. The RX features a low-noise amplifier (LNA), a 60 GHz mixer, a phase-locked loop (PLL), and an IF demodulator. The measured 1-dB compression point at the TX output is 12.6 dBm and the saturated power is 16.2 dBm. The LNA has measured noise figure of 6.5 dB at 60 GHz. Error-free data transmission with a 16 quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal and data rate of 3.6 Gbit/s (without coding 4.8 Gbit/s) over 15 m was demonstrated. This is the best reported result regarding both the data rate and transmission distance in SiGe and CMOS without beamforming.