Measured Noise Figure Research Articles

Dual-Band Low-Noise Amplifier for GNSS Applications

A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively.

A mm‐wave LNA employing current re‐use and non‐linearity cancellation in 28 nm CMOS for automotive RADAR and 6G receivers

AbstractThis letter reports an 85 GHz low noise amplifier (LNA) employing derivative superposition based non‐linearity cancellation and a current re‐use topology. The LNA employs a two‐stage stacked architecture, each featuring neutralized differential pairs utilizing the same DC current. In derivative superposition, an auxiliary branch consisting of neutralized differential pairs cells is added in the LNA in parallel to stage 1 to ensure non‐linearity cancellation. Layout‐based capacitive neutralization is implemented to improve GMAX, resulting in simplified routing, reduced parasitics, and a more compact layout. The proposed LNA is fabricated in TSMC 28 nm CMOS process and achieves a peak gain of 8.4 dB at 84.2 GHz with a measured 3 dB bandwidth () from 79.4 to 92 GHz. The minimum measured noise figure is 12.8 dB. The LNA draws 34 mA of DC current from a 1.2 V supply. The highly linear LNA with IIP3 +6.5 dBm is tailored for automotive RADAR and 6G receivers.

Design of a 2–18 GHz low noise amplifier MMIC with current reused topology

AbstractA 2–18 GHz ultra wideband low noise amplifier (LNA) is illustrated in this letter. The proposed LNA adopts a two‐stage structure, which is composed of a common source amplifying stage and a cascode amplifying stage. By combining band extension matching technique, current reused topology and active bias circuit, the LNA performs excellent in gain, noise figure, power consumption, and immunization against the fluctuation of voltage supply. The LNA is implemented with a 0.18‐μm GaAs pseudomorphic high electron mobility transistor process and has a compact chip area of 1.75 × 1 mm2. The dedicated LNA achieves a measured average gain of 20.7 dB with ±1.5 dB variation all over the ultra‐wide bandwidth of 2–18 GHz. It also has a measured noise figure of lower than 1.7 dB and a measured output 1 dB compression point of higher than 5 dBm in the operating frequency band. The LNA has a low direct current power dissipation of 100 mW under a 5 V voltage supply.

Noise Figure: Estimation of Noise Characteristics of a Radio- Photonic Path Based on the Results of Noise Figure Measurements

In radiophotonic microwave transmission systems, as in any radioelectronic systems, noise characteristics determine the potential of accuracy and range. As a measure of the difference between the noise characteristics of optoelectronic microwave signal converters from ideal ones, the use of the noise figures of the elements included in their composition is proposed. The effect of such a criterion is demonstrated by the example of the optoelectronic microwave oscillator (OEO). Based on the results of the study of the optoelectronic microwave oscillator noise parameters quantitative characteristics of the conversion of the OEO elements noise sources into phase and amplitude fluctuations of the output microwave oscillation are obtained. The analysis of the interaction of the OEO elements noise with the microwave harmonic oscillation is performed. The technique for measuring the noise conversion characteristics using the noise figure has been developed. The results of measuring characteristics of the interaction of harmonic oscillation with the optoelectronic components additive and multiplicative noise of optoelectronic components are presented. Based on the values of the noise figure, the possibilities of reducing the noise levels of microwave signal converters are evaluated and recommendations are made to reduce the influence of the noise.

Noise figure measurement of terahertz mixer

Noise figure measurement of terahertz mixer

K‐band CMOS low‐noise amplifier with 180° phase shift function using cascode structure

AbstractIn this study, a K‐band CMOS low‐noise amplifier (LNA) with a 180° phase shift function is presented to reduce the chip area of the beamforming system. The proposed LNA is composed of three stages, and the last stage is designed with a differential cascode structure for 180° phase shift function. The 180° phase shift function was implemented by dividing one cascode transistor into two transistors. As a result, it is possible to equip the 180° phase shift function without an additional chip area. The LNA was designed with a 65‐nm CMOS process to verify the feasibility of the proposed technique. The core size was 0.66 × 0.41 mm2. The measured phase difference between 0° and 180° phase shift modes was approximately 178° in the operating frequency of 22.0 GHz. The measured noise figure and gain were 3.8 and 12.7 dB, respectively.

Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays

This article presents a chip-to-chip (C2C) interface for constructing reconfigurable phased arrays to be used in fifth-generation (5G)/sixth-generation (6G) wireless systems. The C2C interface further facilitates building phased array panels by allowing the use of grid-based PCB routing, thus providing flexibility in the system design. An eight-element RFIC capable of handling two independent data-streams is fabricated using 45-nm CMOS technology. The RFIC incorporates four C2C interfaces operating at 27 GHz, two C2C interfaces operating at 9 GHz, and a complex baseband (BB) with single-sided bandwidth in excess of 400 MHz. The architecture is tested by flip-chip bonding two fabricated RFICs on an eight-layer Megtron 7 PCB. In this article, only the receiver path of the RFIC and the phased array is described. Performance of both the single RFIC and the combination using the 27-GHz C2C interface is demonstrated using conductive and over-the-air (OTA) measurements. OTA measurements are conducted using 5GNR FR2 OFDM waveforms with a signal bandwidth of up to 800 MHz. The measured RF to BB conversion gain for a single element is larger than 23 dB and the minimum measured noise figure (NF) is 6.2 dB. The nominal dc power consumed by the receiver per element per stream is 116.5 mW. The RFIC occupies a normalized area per element per data stream of 2.7 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> . The RFIC is capable of supporting dual-polarized antennas or in a large-scale panel utilizing the same antenna elements to two independently weighted data streams as part of the hybrid beamforming architecture.

A novel design procedure of a compact-size X-band shunt feedback amplifier

ABSTRACT This paper describes a high-frequency shunt feedback amplifier. A new design procedure is presented based on practical design steps as well as theoretical aspects, such as sizing the transistor, stabilisation, and selecting the values of feedback elements. The amplifier is designed and fabricated using 0.15 μm GaAs technology. It operates in the 7–10 GHz frequency range, with a small signal gain of 11.5 ± 0.5 dB and input and output return losses of less than 6 dB and 7 dB, respectively. Furthermore, for 1 dB and 3 dB output compression points, the maximum measured values are 23.1 dBm and 23.9 dBm, respectively. Besides, the maximum measured value for Power Added Efficiency (PAE) for 1 dB output compression is 27.13% and 48.6% for 3 dB output compression. In addition, the measured Noise Figure (NF) in the frequency band of interest ranges from 3.7 to 4.1 dB. The chip area of the fabricated amplifier is 1.01 mm2.

160 GHz D-Band Low-Noise Amplifier and Power Amplifier for Radar-Based Contactless Vital-Signs-Monitoring Systems.

This paper presents a 160 GHz, D-band, low-noise amplifier (LNA) and a D-band power amplifier (PA) implemented in the Global Foundries 22 nm CMOS FDSOI. The two designs are used for the contactless monitoring of vital signs in the D-band. The LNA is based on multiple stages of a cascode amplifier topology with a common source topology adopted as the input and output stages. The input stage of the LNA is designed for simultaneous input and output matching, while the inter-stage-matching networks are designed for maximizing the voltage swing. The LNA achieved a maximum gain of 17 dB at 163 GHz. The input return loss was quite poor in the 157-166 GHz frequency band. The -3 dB gain bandwidth corresponded to 157-166 GHz. The measured noise figure was between 7.6 dB and 8 dB within the -3 dB gain bandwidth. The power amplifier achieved an output 1 dB compression point of 6.8 dBm at 159.75 GHz. The measured power consumptions of the LNA and the PA were 28.8 mW and 10.8 mW, respectively.

Experimental Measurement of Noise Figure and Radiation Efficiency With the Antenna Y-Factor Method at X-Band

To optimize the design of a high-sensitivity receiver, it is valuable to be able to assign noise budget contributions to various parts of the system. The system noise and aperture efficiency can be characterized using the antenna Y factor method, which has been added recently to the IEEE Recommended Practice for Antenna Measurements, Std 149-2021. We extend the antenna Y factor method by showing that it can be used to measure the noise figure of an active antenna and receiver system.With an additional measurement of the receiver noise, the antenna radiation efficiency can be determined. We demonstrate the extended antenna Y factor method experimentally at X band for antennas under test including a horn with near 100% efficiency, microstrip patch antenna with efficiency near 80%, and a patch antenna array with 40% nominal efficiency.

L Band Phased Array Feed Noise Figure and Radiation Efficiency Measurement with the Antenna Y Factor Method

The noise performance of a high sensitivity, wide-field astronomical phased array feed receiver can be characterized by measurements using the antenna Y factor method. These measurements are used to determine figures of merit for an active array receiver. Antenna elements for the Advanced L Band Phased Array Camera for Astronomy (ALPACA) were measured using the antenna Y factor method to determine the active array and receiver noise figure, the antenna loss, receiver equivalent noise temperature, and radiation efficiency of the system over its 500[Formula: see text]MHz operating bandwidth. The completed ALPACA instrument will feature a fully cryogenic design with both the low-noise amplifiers and array elements cryogenically cooled. The uncooled performance measurements from the antenna Y factor method are used to extrapolate the elements cryogenic radiation efficiency and antenna loss showing that it is expected that the elements will contribute less than 1 K to the overall system noise temperature. These results validate the antenna Y factor method to measure key antenna parameters such as the antenna radiation efficiency and show that the instruments front-end array and electronics meets expected performance targets.

A 140–220-GHz Low-Noise Amplifier With 6-dB Minimum Noise Figure and 80-GHz Bandwidth in 130-nm SiGe BiCMOS

This letter presents an ultra-broadband low-noise amplifier (LNA) with a 3-dB bandwidth of 80 GHz, covering the entire WR5 frequency band (140–220 GHz). Broadband gain and noise performance are obtained through optimal bias selection, dc coupling, and stagger tuning. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Y$ </tex-math></inline-formula> -factor noise figure (NF) measurement results are presented. A NF of 6.9, 6.1, and 8.2 dB is measured at 150, 180, and 210 GHz. Implemented in IHP 130-nm SiGe BiCMOS process, the LNA has a peak gain of 15.5 dB, while consuming 46-mW dc power.

웨이퍼상의 D-대역 회로의 전자파 성능 측정

This paper presents on-wafer measurement methods for the scattering coefficient, power, and noise figure of a semiconductor circuit in the D band (110∼170 GHz). The calibration algorithms for the S-parameter measurement were compared, and the effect of the total coplanar waveguide (CPW) width of the commercial calibration standards was examined. In the power measurement, the accuracy of the measurement value was improved through precision path loss evaluation. In addition, in the noise figure measurement, the system configuration and calibration method are presented, and the path loss compensation is examined. The detailed configuration and considerations for each measurement system are presented, and the measured results of the designed low-noise amplifier (LNA) chip are presented.

220-240-GHz High-Gain Phase Shifter Chain and Power Amplifier for Scalable Large Phased-Arrays

This paper focuses on the design aspects of the key components for a scalable phased-array system over the 200 GHz frequency range. A high-gain phase shifter chain for 220 to 240 GHz frequency range and a high-gain power amplifier (PA) with a high output power are designed in a 0.13-μm SiGe BiCMOS technology. The phase shifter chain includes a low-noise amplifier (LNA), a vector modulator phase shifter (PS), and a gain-enhancing amplifier. The LNA is a five-stage cascode design. The vector modulator core is realized by two variable gain amplifiers based on the Gilbert cell architecture. A four-stage cascode design is used for the gain-enhancing amplifier. The phase shifter chain shows a measured gain of 18 dB at 230 GHz with a 360° phase tuning range and more than 10 dB of gain control. The chip achieves a minimum measured noise figure of 11.5 dB at 230 GHz and shows a wideband noise characteristic. The complete phase shifter chain chip consumes a dc power of 153 mW and occupies a 1.41 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area. A high-power PA that is critical for a large phased-array system is designed. This paper presents a unique 4-way power combining technique utilizing a differential quadrature coupler. The realized balanced PA occupies an area of 0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and shows a measured peak gain of 21 dB at 244 GHz. The PA consumes 819 mW of dc power and delivers a maximum saturated output power ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> ) of 7.1 dBm at 244 GHz and more than 4.3 dBm of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P_sat</i> from 230 to 255 GHz.

A 320 μW Multi-Band Receiver with N-Path Switched-Capacitor Networks

This paper presents a multi-band ultra-low power (ULP) receiver with N-Path Switched-Capacitor (NPSC) networks in 90 nm CMOS process. The NPSC is integrated into the feedback loop of the low noise amplifier (LNA) to flexibly provide narrowband input matching at multiple sub-GHz Industrial, Scientific, and Medical (ISM) bands by adjusting the switching frequency. Moreover, the LNA with an NPSC network is utilized to suppress the out-of-band signal at the input and output of the LNA, simultaneously. In order to achieve an ultra-low power consumption, a sub-threshold LNA and four passive NPSC mixers are implemented in this receiver. The ULP receiver achieves a measured gain of 40±2 dB in ISM bands (430/860/915/960 MHz). The measured noise figure and out-of-band IIP3 are 10±0.5 dB and −0.3±2 dBm, respectively. The ULP receiver chip consumes 320 μW at 0.4 V power supply and occupies a chip area of 0.31 mm2.

A Millimeter-Wave GaN MMIC Front End Module with 5G NR Performance Verification

This paper proposes a millimeter-wave (mmWave) 5G front end module (FEM) based on multiple gallium nitride (GaN) monolithic microwave integrated circuits (MMICs) with 5G new radio (NR) performance verification. The proposed structure is configured by a wide band GaN single-pole double-throw (SPDT) switch MMIC, a GaN low-noise amplifier (LNA) MMIC, and a GaN power amplifier (PA) MMIC with the target operation band from 26.5 GHz to 29.5 GHz. The LNA and PA MMICs are designed with 150 nm GaN/SiC technology, and the SPDT MMIC is designed with 100 nm GaN/Si. The LNA MMIC shows the measured noise figure less than or equal to 2.52 dB within the operation band. The PA MMIC is based on a two-stage configuration and shows about 35 dBm measured saturated power with power-added efficiency better than 34% within the operation band. Also, the SPDT MMIC is based on an artificial transmission line configuration for wideband performance and shows that the measured insertion loss is less than 1.6 dB, and the measured isolation is higher than 25 dB within the operation band. Furthermore, all MMICs are integrated within a single carrier as an FEM and successfully verified by 5G NR test signals.

A 120–140-GHz LNA in 250-nm InP HBT

This letter presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band low-noise amplifier (LNA) in 250-nm InP HBT technology for the next-generation wireless applications. The LNA has a measured peak gain of 13 dB, a 3-dB bandwidth greater than 20 GHz (120–140 GHz), and a measured noise figure (NF) of less than 6 dB in the band. A reduction in the 3-dB bandwidth from simulation was observed during the measurements which was attributed to the substrate waves using full chip electromagnetic (EM) simulation. EM simulations show that a partial or complete removal of the back side metallization of the InP substrate, holes in metal-1 ground plane, or a strategic placement of through-substrate vias suppress these substrate waves. To the authors’ knowledge, this is the first 120–140-GHz LNA in the InP 250-nm HBT technology.

Co‐design of a low noise amplifier with compact substrate integrated waveguide bandpass filtering matching network

This article presents a co-design of a low noise amplifier (LNA) and bandpass filter (BPF) input matching network (IMN) based on quarter-mode and one-eight-mode substrate integrated waveguide (SIW) cavities. The transmission zeros (TZs) of the proposed BPF IMN occur in the stopband and demonstrate improved frequency selectivity compared to conventional methods. Our design can reduce the complexity and circuit sizes of receiving BPFs and LNAs in communication systems, and improve the receiving performance of radio frequency (RF) front-end circuitry. Three different LNAs were fabricated and tested. The proposed LNA features a three-stage compact-size SIW BPF IMN at a center frequency (f0) of 8 GHz. The proposed LNA with a compact SIW BPF IMN exhibits better electrical performance than a conventional LNA (CLNA) with a full-mode (FM) SIW BPF. We found that the small signal gains at f0 of the standalone CLNA, FM SIW BPF cascaded with CLNA, and the proposed LNA were 15.69, 14.72, and 15.18 dB, respectively. The measured noise figure (NF) at f0 of CLNA was 0.86 dB, while the NF of the FM SIW BPF cascaded with CLNA was 2.23 dB, and the NF of the proposed LNA at f0 was 1.71 dB. In addition, the circuit size of the proposed LNA is 48% smaller than that of an FM SIW BPF cascaded with CLNA.

A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL

A fully integrated 490-GHz receiver (RX) adopting a dual-locking receiver-based FLL (DL-RBFLL) is presented. The proposed RBFLL structure saves the power consumption by reusing the existing blocks in RX instead of the power-hungry blocks such as dividers and buffers operating at sub-THz. Contrary to the single-loop implementation, the dual-loop RBFLL, which consists of the coarse and fine locking loops, extends the locking range by six times with negligible additional power dissipation. In the RF front-end (FE), the proposed 2nd-order sub-harmonic mixer (SHM) enhances interport isolation and suppresses the undesired LO leakage using a simple passive network. In the IF path, a 2-stage low-noise amplifier (LNA) followed by a 10-stage programmable gain amplifier provides a controllable gain of 0–80 dB with 4-dB step. An N-path filter, which serves as a high-Q bandpass noise filter, improves SNR in the IF path and thus RX sensitivity. Implemented in a 65-nm CMOS, the 490-GHz RX achieves the measured noise figure of 51.1 dB and noise equivalent power (NEP) of 0.85 pW/Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{0.5}$ </tex-math></inline-formula> for the noise bandwidth of 17 MHz. The estimated sensitivity of the proposed RX is −92.9 dBm for a 1 kHz noise bandwidth, which dissipates 31.8 mW from a 1.2-V supply.

A 6–12 GHz wideband low‐noise amplifier GaAs FET design with 0.8‐dB average NF and 25‐dB gain

AbstractLow‐noise amplifiers (LNAs) with low‐noise performance are critical components in communication systems. However, reaching a high level of performance is difficult. This study introduces a LNA for radio frequency front‐end receivers with a frequency range of 6–12 GHz. The planned LNA contains a two‐stage high‐electron‐mobility transistor cascade amplifier with a minimum measured noise figure of 0.8 dB and a peak gain of 25 dB at room temperature. The proposed LNA is based on a gallium arsenide field‐effect transistor transistor (CE3512K2) because of its good low‐noise performance at microwave frequency bands. The measured results demonstrate that the proposed LNA is perfectly matched over the whole operational frequency spectrum of the input/output ports (|S11|&lt;−10 dB, |S22|&lt;−10 dB). Also, output P1dB and input P1dB are, respectively, +4 and −19 dBm for this design. The suggested LNA is suitable for C and X frequency band applications.