Nickel Silicide Process Research Articles

Improvement of Resistive Switching Characteristics of Titanium Oxide Based Nanowedge RRAM Through Nickel Silicidation

Low operation power and high endurance of resistive random access memory (RRAM) as a synaptic device are critical parameters for in-memory computing applications. Yet, high power consumption and reliability issue of silicon bottom electrode (BE) RRAM hinder its commercialization as a synaptic device. In this experiment, we report on the improvement of switching characteristics of silicon BE nanowedge RRAM via the Nickel (Ni) silicidation process. Existing highly doped Si-BE forms a SiO2 interfacial layer (IL) during a switching layer deposition and increases an effective thickness, leading to increased voltage drop within the RRAM device and large cycle-to-cycle variations. By siliciding the Si-BE with Ni, the issue of IL formation is removed and the resistance of metallic NiSi BE is further reduced compared to Arsenic (As <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ) doped Si BE. Both dc and ac analyses of the fabricated NiSi-BE nanowedge RRAM have shown the reduction of overshoot and switching current down to 55% of the original value. Transmission electron microscopy (TEM) and energy-dispersive spectroscopy (EDS) analysis convinced the formation of NiSi BE. In addition, gradual switching characteristics, uniform low resistance state (LRS), and better endurance of NiSi-BE nanowedge RRAM enable the Si compatible approach to fabricate a large-size RRAM cross-point array for utilization in hardware-implemented neuromorphic computing applications.

A Low-Temperature Nickel Silicide Process for Wafer Bonding and High-Density Interconnects

Wafer-scale heterogeneous integration provides a viable pathway for the development of highly capable microsystems. However, it remains challenging to integrate die-and wafer-level components with a high-density interconnects while minimizing the system volume and within the temperature restrictions imposed by integrated circuits. Advancements in CMOS have motivated the development of low-temperature and low-resistance metal-silicon alloys or silicides. Nickel silicide (NiSi) is a CMOS-compatible material that forms at temperatures and anneal times within the thermal budget of commercial CMOS die and can be implemented with a wide range of nickel and silicon thin-film processing methods. We describe here the development of a 3-D integration strategy utilizing NiSi formation to generate both mechanical bonding and electrical interconnection between wafers. Specifically, we show that our NiSi-based wafer-bonding process is effective below 400 °C, at very short anneal times (minutes), and with a variety of thin-film processing methods. This NiSi-based process offers a robust approach for creating heterogeneously integrated microsystems in a CMOS-compatible fashion.

Electrically Active Defects in Plated Crystalline Silicon n+p Solar Cells: A DLTS Perspective

Cost reduction is one of the major driving forces in the technology development of silicon solar cells. This explains the current interest in the implementation of a copper-based metallization, replacing more expensive Ag contacts [1-3]. In order to prevent the in-diffusion of copper in the underlying silicon substrate, a diffusion barrier, like, e.g., a thin nickel layer is usually deposited. Opening of the passivation layer for contact formation by laser ablation (LA), enables a better controll for narrower line features, compared with standard wet etching. In this work, potential issues with defect fomation associated with laser ablation and metal plating will be studied relying on Deep-Level Transient Spectroscopy (DLTS) [4]. P-doped emitters have been fabricated by POCl3 diffusion into 1-3 Wcm p-type Czochralski silicon substrates. Passivation of the solar cells has been achieved by PECVD of a SiNx:H layer. The dielectric layer at the front was opened by ps UV-laser ablation, using a high fluence (1.08 J/cm2) (hard LA). This was compared with wet etching (WE). Approximately 1 mm of nickel was deposited by light-induced plating, followed by 8 to 10 mm of electroplated copper. More details of the processing have been previously reported [5,6]. Diodes with area of 2 mmx2 mm were laser-cut from the finished solar cells for DLTS, using a Fourier-Transform (FT) system. Temperature (T-) scans have been performed at different bias pulses from a reverse bias VR to a pulse bias VP, for different durations tp. The pulse period was tw. Before cooling the sample, Current-Voltage (I-V) and Capacitance-Voltage (C-V) measurements have been performed at room temperature, the latter at a fixed frequency of 1 MHz. Normal I-V and C-Vs have been obtained (Fig. 1), while rather uniform doping profiles were derived from a 1/C2 versus VR plot (Fig. 2), yielding a doping density in the range of 2×1016 cm-3. The spectra for the wet etched sample in Fig. 3 exhibit two main hole traps in the p-type base layer: a peak at about 80 K and another one at ~150 K. The activation energy of the first trap amounts to 0.17 eV and a hole capture cross section sp of ~7×10-15 cm2. Applying a minority carrier injection pulse to forward VP, reveals a clear electron trap at about the same position in Fig. 4, followed by a second one at higher T. It has been shown elsewhere that the 0.17 eV peak most likely corresponds with the substitutional nickel donor level [5]. The shallow electron trap could well be the double acceptor level of Nis at EC-0.07 eV, while the deeper one may correspond with the first acceptor level. The LA sample exhibits the same 80 K hole trap as after wet etching (Fig. 5), indicating that the nickel-silicidation process introduces nickel in the underlying p-type base, irrespective of the etching. A deeper hole trap at about 200 K is observed as well and could be related to dislocation-related states [5,6]. Further proof of that is the observation of slow capture by the nickel donor level in Fig. 6, which follows an ln(tp) dependence. The capture is much slower than can be expected from the hole capture cross section and indicates that Nis may be trapped in the strain field around the dislocations, penetrating the p-type base. Similar observations have been found in the past for Fe decorating dislocations in p-type silicon [8]. It will, finally, be shown that in both cases, no active copper levels have been detected in the p-type silicon base [5,6].

A Wafer-Scale Ni-Salicide Contact Technology on n-Type 4H-SiC

A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

Ohmic Contact Formation for n+4H-SiC Substrate by Selective Heating Method Using Hydrogen Radical Irradiation

We developed an apparatus for producing high-density hydrogen plasma. We confirmed that the temperatures of transition-metal films increased to above 800?C within 5 s when they were exposed to hydrogen plasma formed using the apparatus. We applied this phenomenon to the selective heat treatment of W/Ni films deposited on n+4H-SiC wafers and formed nickel silicide electrodes. To utilize this method, we can perform the nickel silicidation process without heating the other areas such as channel regions and improve the reliability.

Selective Heating of Transition Metal Usings Hydrogen Plasma and Its Application to Formation of Nickel Silicide Electrodes for Silicon Ultralarge-Scale Integration Devices

We developed an apparatus for producing high-density hydrogen plasma. The atomic hydrogen density was 3.1 × 1021 m?3 at a pressure of 30 Pa, a microwave power of 1000 W, and a hydrogen gas flow rate of 10 sccm. We confirmed that the temperatures of transition-metal films increased to above 800。C within 5 s when they were exposed to hydrogen plasma formed using the apparatus. We applied this phenomenon to the selective heat treatment of nickel films deposited on silicon wafers and formed nickel silicide electrodes. We found that this heat phenomenon automatically stopped after the nickel slicidation reaction finished. To utilize this method, we can perform the nickel silicidation process without heating the other areas such as channel regions and improve the reliability of silicon ultralarge-scale integration devices.

The High Electron Dose of Voltage Contrast Inspection for the Detection of Nickel Silicide Piping Defects

Nickel silicide process is used for the ohmic contact formation, but it could be spiking or piping into the substrate and lead to the device fail by leakage with the high temperature anneal. The piping defect by the nickel silicide process was proposed to be inspected using the electron beam inspection (EBI) at contact tungsten (W) plug CMP. This paper aims at the methodology of piping defect inspection and presents an optimized method to detect true piping defects by high electrons dosage. In this study, The mechanism of the leakage spread effect is described and with a series of experiments during the recipe optimizeation, the electron dosage, landing energy and beam direction were identified to increase the piping defect capture rate.

Pre-Amorphous Implant and Millisecond Annealing for NiPt Sheet Resistance and Junction Leakage Reduction

With the aggressive scale down of MOSFET junction depth, nickel silicide (incorporated with platinum) is finally coming into picture with its low resistivity and silicon consumption. The sheet resistance and junction leakage are always a tradeoff during nickel silicide process development. This article introduces a novel nickel silicide process scheme to achieve low sheet resistance and low junction leakage at the same time. PAI(Pre-Amorphous Implant) is applying for sheet resistance reduction; the well controlled low process temperature during PAI and MSA (Milli-second Annealing) maintain the low junction leakage level.

Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

A silicon nanowire (SiNW) array-based thermoelectric generator (TEG) was assembled and characterized. The SiNW array had pitch of 400 nm, and SiNW diameter and height of <100 nm and ~1 μm, respectively. The SiNW array was formed using a top-down approach: deep-ultraviolet (UV) lithography and dry reactive-ion etching. Specific groups of SiNWs were doped n- and p-type using ion implantation, and air gaps between the SiNWs were filled with silicon dioxide (SiO2). The bottom and top electrodes were formed using a nickel silicidation process and aluminum metallization, respectively. Temperature difference across the TEG was generated with a heater and a commercial Peltier cooler. A maximum open-circuit voltage of 2.7 mV was measured for a temperature difference of 95 K across the whole experimental setup, corresponding to power output of 4.6 nW. For further improvement, we proposed the use of polyimide as a filler material to replace SiO2. Polyimide, with a rated thermal conductivity value one order of magnitude lower than that of SiO2, resulted in a larger measured thermal resistance when used as a filler material in a SiNW array. This advantage may be instrumental in future performance improvement of SiNW TEGs.

Reduction in pn Junction Leakage for Ni-Silicided Small Si Islands by Using Improved Convection Annealing

In conventional self-aligned nickel (Ni) silicide (SALICIDE) process, Ni silicidation is usually carried out by using tungsten–halogen lamp annealing and pn junction leakage current increases with the miniaturization of junction area and depth. The junction leakage is closely related to Ni-silicide thickness determined by absorption coefficient of infrared light from the halogen lamp. We proposed a new method for Ni silicidation based on natural convective heat transfer to the wafer and confirmed that this method can drastically improve the pattern dependence of pn junction leakage because of better uniformity of Ni-silicide thickness independent of pattern size of active areas.

A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance

Work function tuning of nickel silicide (NiSi) gates was utilized to fabricate a novel split-gate MOSFET with improved device performance. The MOSFET with a NiSi split gate has been achieved by implanting antimony into the polysilicon gate from the drain side with a tilt angle, followed by a full nickel-silicidation process. The laterally nonuniform antimony implantation causes the NiSi gate work function to vary from the source side to the drain side due to the dopant segregation effect. Improved current drive and output resistance are observed in the MOSFET with such a NiSi split gate. Metal gate advantages and NiSi process simplicity were also realized in the split-gate process, and gate oxide quality did not degrade due to the low temperature process. This split-gate design is expected to be applicable in the nanoscale regime by optimizing process conditions.

Nickel-silicide process for ultra-thin-body SOI-MOSFETs

A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si 3N 4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices.

NiSi integration in a non-selective base SiGeC HBT process

A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23–24 μΩ cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f t and f MAX, respectively.

Nickel-silicidation process using hydrogen implantation

The effect of hydrogen implantation on a nickel silicide process has been investigated. X-ray photoemission spectroscopy results show that the hydrogen implantation is effective in suppressing the oxidation of NiSi. It is further shown that the junction leakage current of the implanted samples is about one order of magnitude lower than that of the unimplanted ones.

Nickel Silicide Work Function Tuning Study In Metal-Gate CMOS Applications

ABSTRACTMid-gap work function (∼4.7eV) for mono-nickel-silicide (NiSi) was obtained by extrapolating flat band voltages of metal-oxide-semiconductor (MOS) capacitors with different gate oxide thickness. Both silicidation temperature and time can affect the nickel silicide work function as a result of different Ni:Si ratio close to the gate oxide interface. Arsenic implantation into the polysilicon before silicidation can shift the NiSi work function towards the silicon conduction band, which makes it suitable for high performance NMOS applications. The physical mechanism responsible for this work function shift is arsenic pile-up at the oxide interface during the nickel silicidation process. Therefore, dual work function metal gate can be obtained by using a single gate full silicidation process. Silicidation temperature and time also affect the work function shift from arsenic dopant, and the incomplete gate silicidation can have the maximum work function modification effect. Arsenic activation temperature before silicidation was found to have a significant effect on the work function shift. Un-annealed samples exhibit a minimum shift in work function due to the low dopant pile-up concentration at the oxide interface.

Towards implementation of a nickel silicide process for CMOS technologies

In this paper, we review some of the advantages and disadvantages of nickel silicide as a material for the electrical contacts to the source, drain and gate of current and future CMOS devices. We first present some of the limitations imposed on the current cobalt silicide process because of the constant scaling, of the introduction of new substrate geometries (i.e. thin silicon on insulator) and of the modifications to the substrate material (i.e. SiGe). We then discuss the advantages of NiSi and for each of the CoSi 2 limitations, we point out why Ni is believed to be superior from the point of view of material properties, miscibility of phases and formation mechanisms. Discussion follows on the expected limitations of NiSi and some of the possible solutions to palliate these limitations.

Nickel silicidation techniques for strained Si1−xGex, Si1−x−yGexCy, and Si1−yCy alloys material-device applications

A nickel silicide process for Si1-xGex, Si1-x-yGexCy, and Si1-yCy alloy materials compatible with Si technology has been developed. Low-resistivity-phase (12–20 µΘ cm) nickel silicides have been obtained for these alloys with different low sheet-resistance temperature windows. The study shows that thin (15–18 nm) silicide layers with high crystalline quality, smooth silicide surface, and smooth interface between silicide and the underlying material are achievable. The technique could be used to combine the benefits of Ni silicide and Si1-xGex, Si1-x-yGexCy, and Si1-yCy alloys. The technique is promising for Si or Si1-xGex, Si1-x-yGexCy, and Si1-yCy alloy-based metal-oxide semiconductor, field-effect transistors (MOSFETs) or other device applications.