Next-generation Memory Technologies Research Articles

Enhancing ferroelectricity in HfAlOx-based ferroelectric tunnel junctions: A comparative study of MFS and MFIS structures with ultrathin interfacial layers

This study explores the potential advantages of metal–ferroelectric–insulator–semiconductor (MFIS) structures compared with established metal–ferroelectric–semiconductor (MFS) and metal–ferroelectric–metal structures in the context of nonvolatile memory devices. Despite the superior performance of MFS structures in terms of electric field maintenance, switching speed, and power consumption, the presence of interface-related issues between the ferroelectric material and the semiconductor may degrade device performance. We propose an MFIS structure incorporating ultrathin interfacial layers (ILs) of SiO2, HfO2, and ZrO2 to address these issues. These insulator layers enhance device endurance by reducing physical stress and trap density at the interface, thereby improving electrical performance and long-term stability. Moreover, the presence of an IL reduces charge leakage between the ferroelectric layer and semiconductor, contributing to the resolution of the sneak path current problem. An additional feature of MFIS devices is their self-rectifying behavior, simplifying circuit design and manufacturing processes by eliminating the need for an external rectification circuit, consequently reducing costs. Through a series of experiments, this study evaluates the performance of the MFIS structure, investigates the ferroelectric properties of HfAlOx-based FTJs, and examines the conduction mechanism of the MFIS structure. By comparing the o-phase of MFS, SiO2, HfO2, and ZrO2 devices via grazing incidence X-ray diffraction (GIXRD) and using the positive-up-negative-down method to extract polarization and coercive voltage, we provide a comprehensive investigation of the impact of ultrathin ILs on ferroelectric properties. This research aims to offer valuable insights into the advancement of memory device technologies, presenting the MFIS structure as a promising platform for next-generation memory technologies. Further sections will elaborate on the experimental setup, methodology, and detailed study findings.

Architecture-level energy model for high-capacity STT-MRAM memory

ABSTRACT Nowadays, STT-MRAM has emerged as one of the leading contenders for next-generation memory technologies. However, STT-MRAM still exhibits high energy consumption due to its peripheral circuits, including the read/write and the sample amplifier (SA) circuits. Therefore, it is crucial to accurately evaluate the energy consumption of memory architectures during the early stages of the design process. Traditionally, energy evaluation can be conducted using the NVSim platform. However, the peripheral read/write circuitry of STT-MRAM undergoes iterative improvements, which cannot be promptly incorporated into NVSim. To addreGss this limitation and to enable comprehensive energy consumption evaluations spanning from device-level to architecture-level for STT-MRAM, an architecture-level energy consumption model is proposed in this paper. The model offers high accuracy and flexibility for the STT-MRAM memory array structure, abstracting the influences of read/write circuits for power evaluations. Comparative analysis is performed between the proposed model and the traditional approaches. When estimating a memory array with 128 × 64, the deviation using the proposed model is less than 2%, showing improved accuracy compared to that with analytical formulas. Notably, the proposed model offers up to 97% time savings in the whole circuit simulation, thus enhancing efficiency in the design and evaluation process.

Next generation synthetic memory via intercepting recombinase function

Here we present a technology to facilitate synthetic memory in a living system via repurposing Transcriptional Programming (i.e., our decision-making technology) parts, to regulate (intercept) recombinase function post-translation. We show that interception synthetic memory can facilitate programmable loss-of-function via site-specific deletion, programmable gain-of-function by way of site-specific inversion, and synthetic memory operations with nested Boolean logical operations. We can expand interception synthetic memory capacity more than 5-fold for a single recombinase, with reconfiguration specificity for multiple sites in parallel. Interception synthetic memory is ~10-times faster than previous generations of recombinase-based memory. We posit that the faster recombination speed of our next-generation memory technology is due to the post-translational regulation of recombinase function. This iteration of synthetic memory is complementary to decision-making via Transcriptional Programming – thus can be used to develop intelligent synthetic biological systems for myriad applications.

(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories

Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs are integrated at the same advanced technology nodes as SRAMs [1]. In this talk, we will discuss the potential path for FEFET toward fulfilling this vision, by addressing the outstanding technological challenges: ultra-fast read-after write, reliability, voltage scaling and variation. To that end, our recent exposition on the trap and reliability physics of FEFETs will highlighted. We will highlight, based on newly developed experimental schemes, how the simultaneous capture and emission of electrons and holes in write cycles occur at the interface and the grain boundaries in the time domain, where in the band-diagram, these traps (acceptors and donors) are located and how exactly they result in the degradation of the read speed and reliability with continued write cycling. Based on these insights, we move on show how engineering the interfacial layer and the ferroelectric grain structure can enable ultra-fast read-after write and write voltage and dramatic improvements in reliability and variation, towards achieving a high-density, ultra-high speed memory technology.This research is supported by the National Science Foundation, the Defense Advanced Research Program Agency (DARPA), the Semiconductor Research Corporation (SRC) - Global Research Collaboration (GRC) program, the Applications and Systems-Driven Center for Energy-Efficient Integrated Nano Technologies (ASCENT), one of six centers in the Joint University Microelectronics Program (JUMP), a SRC program sponsored by the DARPA, and an Intel Rising Star award. [1] Mikolajick, T., Schroeder, U. & Slesazeck, S. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron Devices 67, 1434–1443 (2020).[2] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology." Nature Electronics 3.10 (2020): 588-597.

Changeable electroresistance in Pt/Pb(Zr,Ti)O3/(La,Sr)MnO3 tunnel junctions and memristive properties for synaptic plasticity emulation

Ferroelectric tunnel junctions (FTJs) are promising candidates for the next-generation memory technologies. The electroresistance mechanism, however, has been reported not only from the polarization-modulation of barrier profiles. Electrical migration of charged defects has also been observed as a possible origin for the resistive switching. Here, we achieve two kinds of electroresistance behaviors in Pt/Pb(Zr,Ti)O3/(La,Sr)MnO3 tunnel junctions by introducing oxygen vacancies in the Pb(Zr,Ti)O3 barrier. The oxygen vacancies are observed by x-ray photoelectron spectroscopy, and their effects on the widely adopted piezoresponse force microscopy characterizations of ultrathin ferroelectric films have been analyzed by AC voltage-dependent hysteresis loops. For the Pt/Pb(Zr,Ti)O3/(La,Sr)MnO3 device that is modulated by the polarization reversal, a counterclockwise resistance–voltage (R–V) relationship is observed due to the tunneling between high and low barriers, whereas the R–V hysteresis loop is changed to clockwise with the existence of oxygen vacancies, in which conductive filaments are formed in the Pb(Zr,Ti)O3 barrier. However, such an ionic electroresistance is not stable during repetitive switching. Further investigation on memristive behaviors is, thus, performed on the ferroelectric-controlled Pt/Pb(Zr,Ti)O3/(La,Sr)MnO3 tunnel junctions. An excellent linearity is achieved in continuous resistance change owing to the nucleation-limited-switching mode of domain switching in the Pb(Zr,Ti)O3 barrier, giving rise to spike-timing-dependent plasticity behaviors for the Hebbian rule of learning and memory. These results provide insight into the distinguishing of ferroelectric and ionic contributions in electroresistance of FTJ devices, facilitating deep understanding of nonvolatile resistive memories.

Modeling approach helps describe next-generation memory technologies

Predictions describing current-driven ‘domain-wall’ dynamics on 2D materials may revolutionize information storage.

Impact of Process Variability on Write Error Rate and Read Disturbance in STT-MRAM Devices

Spin-transfer torque magnetic random-access memory (STT-MRAM) is the most promising next-generation memory technology that combines the advantages of mainstream memory technologies, such as SRAM, DRAM, and flash. In the STT-MRAM, a magnetic tunnel junction (MTJ) is used as a bit-cell to store the data, and its magnetic properties have a critical role in thermal noise-aware STT-switching operations. This work analyzes the impact of MTJ material and geometric parameter variations, such as saturation magnetization (MS), magnetic anisotropy (HK), damping factor (α), spin polarization efficiency factor (η), oxide thickness (tOX), free layer thickness (tF), tunnel magnetoresistance (TMR), and cross-sectional area of free layer (AF) variations on write error rate (WER) and read disturbance rate (RDR) for reliable write and read operations, respectively. To evaluate the scalability of MRAM devices, we investigate both WER and RDR with a wide range of MTJ diameters between 90 and 30 nm, which corresponds to mainstream technology nodes from 40 up to 14 nm advance node. In our work, the Fokker-Planck (FP) numerical approach is mainly utilized for an efficient analysis, which allows for parametric variation and evaluates its impact on switching. Although the impact of material and geometric parameter variations on WER is decreased as MTJ scales down from 90 to 30 nm, the variation effect can be still critical with small MTJ diameter, and the most significant influential variation is η, MS, HK, and α in that order. By contrast, the impact of material and geometric parameter variation on RDR increases in MTJ scaling, and we show that negative variations of HK and MS could be a critical bottleneck in 30 and 40 nm MTJ diameters. Our work finally emphasizes the necessity of the WER and RDR analysis by considering the parameter variation in MTJ scaling for practical STT-MRAM development.

Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, phase change memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multilevel cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. The simulation results show a reduction of about $10^{5}$ X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.

Modelling resistive and phase-change memory with passive selector arrays: a MATLAB tool

Memristor devices are crucial for developing neuromorphic computers and next-generation memory technologies. In this work, we provide a comprehensive modelling tool for simulating static DC reading operations of memristor crossbar arrays that use passive selectors with matrix algebra in MATLAB. The software tool was parallel coded and optimised to run with personal computers and distributed computer clusters with minimised CPU and memory consumption. We study the effect of changing the line resistance, array size, voltage selection scheme, selector diode’s ideality factor, reverse saturation current and sense resistance on the electrical behaviour and expected sense margin of a conventional one-diode-one-resistor crossbar arrays. We then investigate the effect of single- and dual-side array biasing and grounding on the dissipated current throughout the array cells. The tool we offer to the memristor community and the studies we present enable the design of larger and more practical memristor arrays for application in data storage and neuromorphic computing.

A Universal Strategy for Stretchable Polymer Nonvolatile Memory via Tailoring Nanostructured Surfaces

Building stretchable memory is an effective strategy for developing next-generation memory technologies toward stretchable and wearable electronics. Here we demonstrate a universal strategy for the fabrication of high performance stretchable polymer memory via tailoring surface morphology, in which common conjugated polymers and sharp reduced graphene oxide (r-rGO) films are used as active memristive layers and conductive electrodes, respectively. The fabricated devices feature write-once-read-many-times (WORM) memory, with a low switching voltage of 1.1 V, high ON/OFF current ratio of 104, and an ideal long retention time over 12000 s. Sharp surface-induced resistive switching behavior has been proposed to explore the electrical transition. Moreover, the polymer memory show reliable electrical bistable properties with a stretchability up to 30%, demonstrating their great potential candidates as high performance stretchable memory in soft electronics.

TiNx/Hf0.5Zr0.5O2/TiNx ferroelectric memory with tunable transparency and suppressed wake-up effect

The discovery of HfO2-based ferroelectric (FE) films gives FE memory devices great potential for the next-generation memory technology. In this letter, TiNx with varying nitrogen atomic contents was demonstrated as electrodes of FE Hf0.5Zr0.5O2 memory devices on quartz substrates for transparent memory applications. The transmittance and reflectance from 350 nm to 2500 nm of the TiNx/Hf0.5Zr0.5O2/TiNx structures generally increased and decreased, respectively. Selectivity between the visible and infrared light altered as the N content is increased. When the N2 ratio increases from 0% to 30%, the transmittance selectivity between 1064 nm (infrared) and 532 nm (green) lights increases from 79.6% to 105.3%, while the reflectance selectivity decreases from 107.9% to 48.9%. The polarization cycling performance of FE TiNx/Hf0.5Zr0.5O2/TiNx was explored up to 107 times. The devices with N-rich TiNx electrodes showed suppression of the wake-up effect during cycling. The transient current loops and atomic-fraction depth profiles of capacitors were inspected as well. The results indicated that there were fewer oxygen-vacancy defects in the as-grown N-rich devices and no influential redistribution of oxygen-vacancy defects during the cycling.

High Resolution Imaging of Chalcogenide Superlattices for Data Storage Applications: Progress and Prospects

Phase‐change materials (PCMs) based on Ge–Sb–Te alloys are a strong contender for next‐generation memory technology. Recently, PCMs in the form of GeTe–Sb2Te3 superlattices (CSLs) have shown superior performance compared to ordinary PCM memory, which relies on switching between amorphous and crystalline phases. Although detailed atomic structure switching models have been developed with the help of ab‐initio simulations, there is still fierce scientific debate concerning the experimental verification of the actual crystal structures pertaining to the two CSL memory states. One of the strongest techniques to provide this information is (scanning) transmission electron microscopy ((S)TEM). The present article reviews the analyses of CSLs using TEM‐based techniques published during the last seven years since the seminal 2011 Nature Nanotechnology paper of Simpson et al., showing the superior performance of the CSL memory. It is critically reviewed what relevant information can be extracted from the (S)TEM results, also showing the impressive progress that has been achieved in a relatively short time frame. Finally, an outlook is given including several open questions. Although debate on actual switching mechanism in CSL memory is clearly not settled, still there is consensus in this field that CSL research has a bright future.

Memristive devices based on emerging two-dimensional materials beyond graphene.

With the explosion of data in the information universe and the approaching of fundamental limits in silicon-based flash memories, the exploration of new device architectures and alternative materials is necessary for next-generation memory technology. Accordingly, emerging two-dimensional (2D) material-based memristive devices have attracted increasing attention due to their unique properties and great potential in flexible and wearable devices, and even neuromorphic computing systems. Herein, we provide an overview of the recent progress on memristive devices based on 2D materials beyond graphene. The device structures and choice of active materials and electrodes materials are summarized for various types of 2D material-based memristive devices. Following the discussion and classification on the device performances and mechanisms, the challenges and perspectives on future research based on 2D materials are also presented.

Chemical Vapor-Deposited Vanadium Pentoxide Nanosheets with Highly Stable and Low Switching Voltages for Effective Selector Devices.

Recently, attempts to overcome the physical limits of memory devices have led to the development of promising materials and architectures for next-generation memory technology. The selector device is one of the essential ingredients of high-density stacked memory systems. However, complicated constituent deposition conditions and thermal degradation are problematic, even with effective selector device materials. Herein, we demonstrate the highly stable and low-threshold voltages of vanadium pentoxide (V2O5) nanosheets synthesized by facile chemical vapor deposition, which have not been previously reported on the threshold switching (TS) properties. The electrons occupying trap sites in poly-crystalline V2O5 nanosheet contribute to the perfectly symmetric TS feature at the bias polarity and low-threshold voltages in V2O5, confirmed by high-resolution transmission electron microscopy measurements. Furthermore, we find an additional PdO interlayer in V2O5 nanodevices connected with a Pd/Au electrode after thermal annealing treatment. The PdO interlayer decreases the threshold voltages, and the Ion/ Ioff ratio increases because of the increased trap density of V2O5. These studies provide insights into V2O5 switching characteristics, which can support low power consumption in nonvolatile memory devices.

PCMLogging: Optimizing Transaction Logging and Recovery Performance with PCM

Phase-change memory (PCM), as one of the most promising next-generation memory technologies, offers various attractive properties such as non-volatility, byte addressability, bit alterability, and low idle energy consumption. Recently, PCM has drawn much attention from the database community for optimizing query and transaction performance. As a complement to existing work, we present PCMLogging, a novel logging scheme that exploits PCM for both data caching and transaction logging to minimize I/O accesses in disk-based databases. Specifically, PCMLogging caches dirty pages/records in PCM and further maintains an implicit log in the cached updates to support database recovery. By integrating log and cached updates, PCMLogging enables simplified recovery and prolongs PCM lifetime. Furthermore, using PCMLogging, we develop a wear-leveling algorithm, that evenly distributes the write traffic across the PCM storage space, and a cost-based destaging algorithm that adaptively migrates cached data from PCM to external storage. Compared to classical write-ahead logging (WAL), our trace-driven simulation results reveal up to 1 $\sim$ 20X improvement in system throughput.

Next-Generation Memory [Guest editors' introduction

A defining component of today's mobile devices and computing systems, memory technology is both a solution and a bottleneck, and industry is racing to redefine its use for future systems. The Web extra at http://youtu.be/pQvE6g8zUho is a an audio interview in which guest editor Simon S.Y. Shim talks about next-generation memory technologies with Alan Niebel, founder and chief executive officer for Web-Feet Research, a nonvolatile memory and storage semiconductor market research company.

Flash challengers work well at nanoscale

A team of scientists at Stanford University has used carbon nanotubes to create nanoscale versions of two next-generation memory technologies. The results help demonstrate that alternatives to flash memory will perform well even when scaled down to below 10 nanometers in size-a range where silicon memories won't function.