Neutral Point Clamped Topology Research Articles

Comprehensive modeling and formulation of split DC link capacitors balancing problem in Three-Phase Three-Level bidirectional AC/DC converters operating with arbitrary power factor

Three-phase three-level AC/DC and DC/AC converters have demonstrated several advantages over their classical two-level counterparts such as better efficiency, enhanced total harmonic distortion, lower dv/dt and lesser overall chip area. T-type and neutral point clamped (NPC) topologies dominate the family of three-phase three-level converters, widely used in 10kVA – 100kVA power range. However, control of three-level converters is more complicated than of their classical two-level counterparts due to necessity of adopting an additional voltage loop, aimed to balance partial split DC link voltages. Moreover, the latter contain multiples of triple-base-frequency harmonic ripple even under balanced AC-side operation (this does not happen in two-level converters), which should be minimized by the balancing loop mentioned above. The nature of partial DC link ripple formation was analyzed in-depth for unity power factor operation, yet hardly extended to non-unity power factor cases. Moreover, inaccurate conclusions were drawn in some of the related studies. Consequently, this paper focuses on comprehensive modeling and formulation of split DC link capacitors balancing problem in three-phase three-level bidirectional AC/DC converters operating with arbitrary power factor. Analytical expression for dynamics of partial DC link voltages difference is derived and studied in depth. The relation between zero-sequence component of modulation signals and neutral point current, tending to unbalance partial DC link voltages is explicitly established for arbitrary power factor values. Practical cases of restricted and unrestricted zero-sequence component of modulation signals are presented. Analytical predictions are shown to be fully supported by simulations based on both switching-cycle-averaged and full switched converter models. Experimental results obtained employing a 10kVA T-type converter prototype operating with restricted zero-sequence component of modulation signals under different power factor values are also given to further validate the presented methodology.

Active Neutral Point Clamped Three-level Synchronous Space Vector Width Modulation Research

Active neutral point clamped (ANPC) topology is widely studied because it makes loss equalization possible. To reduce the switching frequency of high power traction systems, the multi-mode modulation strategy is used in many modulation methods. To reduce the fluctuation problem when switching between different carrier ratios in multi-mode synchronous space vector pulse width (SSVPWM) modulation algorithm, this paper studies the stator flux under different modes and proposes a multi-mode SSVPWM switching strategy based on the pulse insertion method. In this strategy, the stator flux deviation of two modes before and after the switching point is calculated online and the switch sequence is inserted at the switching time to compensate, and the smooth transition between different modes is realized with experimental verification of validity.

State-of-the-Art 800 V Electric Drive Systems: Inverter–Machine Codesign for Energy Efficiency Optimization

This paper introduces a state-of-the-art inverter–machine codesign methodology for achieving an energy-efficient electric drive system. The methodology is applied in an optimal design case study with the context of the latest trend in the 800 V system. To reduce the voltage rating, a three-level active neutral point clamped topology is utilized in the inverter design, incorporating silicon carbide technology for high-speed operation. This combination allows for efficient power conversion with reduced losses. In the machine design, the increased number of poles that can be achieved in the design phase, along with the utilization of high-speed switching frequencies, enables the development of more efficient machines. Based on the design of the experiment method, by optimizing the parameters of both the inverter and machine simultaneously, using a cosimulation model, the 7.7% of total energy loss during drive cycle operation can be improved.

Development and testing midpoint voltage balance algorithms of three-level inverters

Nowadays, the use of inverters is increasing in more and more applications. Environmental awareness is becoming a trend, so more and more people install solar energy systems on their houses, which also require the use of inverters. Higher power levels have led to the emergence of three-level inverters which has opened up new challenges, such as the issue of midpoint voltage balancing. This paper discusses voltage balancing and voltage ripple reduction techniques for three-level inverters with Neutral-Point Clamped (NPC) topology. The balancing is based on injecting zero-sequence voltage component in carrierbased modulation. The viability of the modulation techniques are verified by computer simulation and then tested on hardware.

Performance analysis and control of a novel 7‐level active neutral point clamped (ANPC) topology

AbstractThis paper introduces a novel 7‐level active neutral‐point clamped (ANPC) switched capacitor multilevel inverter (SCMLI) with voltage‐boosting capabilities. The proposed converter can produce seven levels and a voltage boosting of 1.5 times with a single dc source. For boosting the voltage, two self‐balanced switched capacitors and two dc link capacitors with active neutral point are used with nine switches. For controlling the output voltage, the level‐shifted modulation technique and modified nearest level control technique is used. The performance of the converter is evaluated with both modulation techniques. The operation of the proposed SCMLI and the design of capacitors for the proposed circuit is discussed in detail. The proposed topology can eliminate the leakage current and has reduced voltage stress across switches which makes it suitable for solar photovoltaic applications. The proposed converter is compared with some other recently introduced converters in terms of voltage gain, the number of components used, and the voltage stress across the switches. For verifying the performance of the proposed circuit, the experimental and simulation results are presented in the paper. The experimental results closely agree with the simulation and theoretical studies. The total harmonic distortion (THD) in the output voltage and efficiency is compared with both modulation techniques.

Low-Complexity Finite Set Model Predictive Control for Split-Capacitor ANPC Inverter With Different Levels Modes and Online Model Update

In this article, an improved finite-control-set model predictive control (FCS-MPC) is presented for an active neutral point clamped (ANPC) topology. The considered converter significantly reduces the required power electronics components compared with other common dc-link converters, where only seven active switches, one bidirectional switch, and two floating capacitors (FCs) are employed to produce nine levels in the phase voltage. The developed FCS-MPC handles three control objectives with only one weighting factor, namely, current control, FC balancing, and NP potential stabilization, which reduces the cumbersome effort required for weighting factors coordination. In addition, the number of iterations required to identify the optimal vector is significantly reduced, which, in turn, reduces the execution time of the algorithm. The proposed control method empowers the considered converter to operate in different modes under the faulty condition of the bidirectional switch without any structure modification, which guarantees continuous operation of the converter while ensuring the balancing of FCs and dc-link capacitors in all operating modes. The sensitivity of the proposed FCS-MPC to parameter mismatch, which is a basic issue of MPC-based techniques, is tackled by employing an extended Kalman filter (EKF) to online estimate the system parameters. The proposed FCS-MPC algorithm is experimentally validated and compared with the conventional FCS-MPC method under different operating conditions.

Clamping Modulation Scheme for Low-Speed Operation of Three-Level Inverter Fed Induction Motor Drive With Reduced CMV

This article introduces a family of carrier-based pulse width modulation (PWM) schemes for three-level (3 L) inverter fed motor drive for low-speed operation. The proposed PWM in dual-inverter topology (DIT) simultaneously clamps two phases of each inverter throughout the fundamental cycle, which reduces the switching transition in the pole voltage and common-mode voltage (CMV). Four PWM variants in the family (i.e., PWM-1–PWM-4) are discussed and compared with conventional discontinuous PWM schemes. A mapping of the gating pulse is derived to extend the proposed PWM to a classical 3 L inverter fed star-connected motor drive. The gating pulses are generated using triangular carrier comparison with synchronous sampling. The steady-state and dynamic performances of PWM are validated both in DIT fed open-end winding induction motor (IM) drive and neutral point clamped (NPC) inverter fed star-connected IM drive. It is observed that the proposed PWM gives inherent capacitor voltage balance in the NPC topology. PWM-1 has a higher linear modulation range than conventional zero clamp PWM and leads to reduced CMV in the NPC topology. PWM-2 and PWM-3 give reduced CMV in DIT. PWM-4 has fault tolerance to single-phase open-switch and short-switch failure in DIT.

A Review of Open-Circuit Switch Fault Diagnostic Methods for Neutral Point Clamped Inverter

Due to numerous advantages, a neutral point clamped (NPC) inverter is a preferred choice for high-power applications and renewable technology. The reliability of the NPC inverter is a major concerning factor during the assessment of system performance as power semiconductor switches are vulnerable to abnormal conditions. Open-circuit (OC) switch faults are not as dangerous as short circuit (SC) faults but eventually have enough potential to cause cascaded failure to other components in the system and thus need to be supervised carefully. The OC faults result in a distortion of voltage and current signals in the NPC converter. Based on these signals, over the past few years, many efforts have been made to identify and localize the OC switch fault to the switch level in the NPC topology. In this paper, a review of different OC switch fault diagnostic methods is provided. Starting from the NPC inverter operation under healthy and faulty conditions, the various possible and unavailable switching states along with the deviation in pole voltage under different switch fault conditions is discussed. Then, based on the approach used for system-based fault detection, the OC fault detection methods are classified. The various OC methods are further discussed on the basis of signal, i.e., current, voltage or a combination of both signals used as a signature for fault detection. Emphasis is given to the principle involved, diagnostic variables utilized, the implementation approach and the diagnostic time required. Finally, the approaches are tabulated so as to provide a quick reference for NPC fault diagnostics.

Detailed Power Loss Analysis of T-Type Neutral Point Clamped Converter for Reactive Power Compensation

The paper presents an analysis of power losses in a three-phase T-type neutral point clamped converter with insulated gate bipolar transistors. The paper’s main aim is to perform a detailed analysis of power losses in the converter operating as an active power filter. The study is based on the use of characteristics of semiconductor devices provided by the manufacturer in the module datasheet. Thanks to the analysis, it is possible to recognise the value of power losses, which facilitates the design of the converter cooling system. Identifying how power losses are distributed between the module switching devices is also possible. Power losses are shown as functions of the output current and module temperature. The analysis results were successfully verified by measuring power losses using a laboratory model of the converter with rated currents of 10 and 20 A. The obtained results indicate relatively low power losses and a relatively even distribution of power losses between the semiconductor devices. This is a superior feature of the three-level T-type neutral point clamped converter topology.

FAULT DETECTION BASED ON THE DISCRETE WAVELET TRANSFORM FOR THE CONVERTER OF A WIND POWER GENERATOR SYSTEM OPERATING UNDER DISTURBANCES IN THE GRID

In this work, an open-circuit fault detection scheme for the converter of a wind power generation system is proposed and evaluated, which is robust to false detections under grid disturbance conditions such as sags and swells. The wind energy system is composed of a doubly-fed induction generator (DFIG) that supplies energy to the electrical grid through a power electronics converter based on the neutral point-clamped topology in a back-to-back configuration (NPC-BTB). The converter operates with a field-oriented-control (FOC) scheme, whereas the fault detection method is based on the processing of the current signals flowing through the converter at the rotor and stator sides of the generator using the discrete wavelet transform (DWT) with the Haar and Daubechies4 wavelet types. The fault detection scheme is evaluated verifying that false detections do not arise, analyzing cases where magnitude variations in the grid voltage of 15%, 30% and 50% occur, with respect to the nominal operating condition.

Fault location method of IGBT short-circuit for a grid-tied Neutral-Point-Clamped inverter system

For the Neutral-Point-Clamped (NPC) three-level grid-tied inverter, when IGBT short-circuit happens, the hardware protection would be triggered immediately to block all drive signals. After the system shuts down the fault location cannot be learned. This paper proposes a short-circuit fault location method for the internal switches of the NPC topology, based on the current loop analysis after system shuts down. The proposed method does not need to add additional sensors, only by means of the existing monitoring data can be completed fast diagnosis. The experimental results verify the feasibility and effectiveness of the proposed fault location method.

Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm2.

Novel Single-Phase Grid-Tied NPC Five-Level Converter with an Inherent DC-Link Voltage Balancing Strategy for Power Quality Improvement

This paper presents a novel single-phase grid-tied neutral-point-clamped (NPC) five-level converter (SPFLC). Unlike the literature on five-level NPC topologies, the proposed one is capable of inherently balancing the voltage of the DC-link split capacitors. For this purpose, a simple Multicarrier Phase Disposition (MPD) Pulse Width Modulation (PWM) technique is used, thus avoiding both complex modifications to the Space Vector Modulation (SVM) and offset voltage injections into the carrier based (CB) PWM, as commonly done in most conventional balancing algorithms. Bearing in mind that the proposed balancing strategy only requires measuring the capacitors’ voltages and the sign of the converter output current, it has a very low complexity. The developed strategy is not only straightforwardly implemented but is also very effective for obtaining symmetrical and undistorted voltage levels from the proposed multilevel converter, as well as for significantly improving the power quality of the SPFLC output voltage and, in turn, of the grid current. The simulation results obtained with MATLAB-SimPowerSystems as well as the experimental results obtained with the prototype built in the laboratory validate the topology of the proposed NPC five-level converter and the voltage balancing strategy, by showing a good performance under step-changes and exhaustive operating test conditions.

A new family of boost active neutral point clamped inverter topology with reduced switch count

A new family of inverter topology for active neutral point clamped (ANPC) is proposed. The traditional ANPC gives the output voltage of half the input voltage which necessitates the use of higher input dc-link voltage. To fix this problem, a floating capacitor is used to increase the voltage of the output, which decreases the dc-link requirement. Moreover, no sensors are needed to stabilize the floating condenser for the proposed topology, which minimizes inverter complexities. The neutral point is connected directly to the load terminals, which decreases the leakage current and makes it suitable for solar PV integration. Two modes of operation of the proposed topology have been discussed while considering the voltage of the floating capacitor used in the topology. Furthermore, two extensions of the proposed topology with generalized structure have also been provided in the paper. A detailed comparison with similar topologies has been provided. The level-shifted pulse width modulation technique has been used for the control of the proposed active neutral point clamped topology. In order to illustrate the idea of the proposed active neutral point clamped inverter, the theory of operation and analysis is accompanied by simulation, and experimental waveforms obtained from a laboratory prototype are provided.

A Proposed Five-level Neutral Point Clamped Inverter

This paper presents a proposed five-level inverter based on conventional five-level Neutral Point Clamped (NPC) topology which is a type of Multilevel Inverters (MLIs). MLI is a great solution for high power application in addition to medium power, low power and renewable energy applications. The proposed topology reduces the number of input DC sources as compared with the conventional five level NPC topology. Also, this circuit reduces the conduction losses by reducing number of switches that turned on in each mode. The circuit operation analysis in each mode is illustrated. A proper modulation strategy based on Pulse Width Modulation PWM is applied on the proposed circuit. The simulation of the proposed circuit is carried out in MATLAB/SIMULINK environment. The results show a comparison between conventional five-level NPC and modified circuits which illustrate a good performance for the proposed one which make it suitable for many applications such as photovoltaic systems.

FS-MPC Based Thermal Stress Balancing and Reliability Analysis for NPC Converters

Active thermal control has been introduced to regulate the steady state and reduce the transient thermal-mechanical stress in power electronic modules. Specifically, it can equally distribute the temperature among the devices, thereby better distributing the stress among a set of devices and reducing the failure probability in the most thermally-stressed devices. This is of great importance for multilevel topologies and in particular for the Neutral Point Clamped (NPC) topologies, which have an inherent thermal unbalance among devices of the same phase. In hybrid structures, whereby Si and SiC devices are mixed to achieve a better trade-off between efficiency and cost, this problem is even worse due to technology differences. This paper investigates the advantages introduced by using Finite-Set Model Predictive Control (FS-MPC) algorithms designed for achieving a balanced device junction temperature in hybrid NPC and Active-NPC converters. Moreover, a novel setup composed by a hybrid ANPC based power modules is used to experimentally validate the presented FS-MPC algorithm. A lifetime estimation is performed for the two topologies to highlight the long-term benefits of FS-MPC algorithm in these hybrid topologies for UPS applications.

Control Design and Experimental Validation of a HB-NPC as a Shunt Active Power Filter

This work presents the design of a control law based on the average model of a shunt active power filter considering an H-bridge neutral point clamped topology and its experimental validation. Therefore, the proposed controller is formed by three control loops, namely current (inner), regulation (outer), and balance control loops. The current loop aims to compensate both the displacement power factor and the harmonic distortion produced by nonlinear loads connected to the point of common coupling. To deal with harmonic current distortion, the current loop involves an adaptive mechanism based on a bank of resonant filters tuned at odd harmonics of the fundamental grid frequency. The regulation and balance loops are aimed to maintain the voltage of the capacitors forming the DC-link at a desired constant level. For this, proportional-integral controllers are designed. The design of all three loops considers the average model of the system. The performance of the proposed multi-loop control law is evaluated through numerical results and real-time experimental implementation, both considering a 2 kW academic benchmark with a constant switching frequency of 7 kHz. In order to provide harmonic distortion, a nonlinear load based on an uncontrolled diode bridge rectifier is considered. Additionally, step-load changes from 0.5 kW to 1 kW are considered for the nonlinear load. As a result, a suitable current tracking, voltage regulation, and balance are observed despite parametric uncertainties, load variations, and harmonic distortion. As a consequence, in steady state, simulation results indicate that the compensated grid current THD is 1.75%; meanwhile, the nonlinear load current THD is 52.5%. Experimental results indicate that the compensated grid current THD is 2.32%; meanwhile, the nonlinear load current THD is 53.8%.

A Topology Synthetization Method for Single-Phase, Full-Bridge, Transformerless Inverter with Leakage Current Suppression—Part II

This paper proposes a topology derivation methodology to achieve small leakage current or zero leakage current for photovoltaic application. The core of the proposed method is a unified topology model and MN principle to show how to derive all possible topologies based on unipolar sinusoidal pulse width modulation (USPWM) and double-frequency USPWM (DFUSPWM). Part II of this paper discusses the topology synthetization method to achieve zero leakage current. Two types of neutral point clamped (NPC) topologies based on USPWM and DFUSPWM are elaborated. Two possible connections for the NPC cell are introduced, and detailed NPC topology derivation procedures are also provided. All existing NPC topologies are derived, and twenty-two new NPC topologies are found based on the new topology derivation methodology for a single-phase, full-bridge, transformerless inverter.

MPC Algorithm With Reduced Computational Burden and Fixed Switching Spectrum for a Multilevel Inverter in a Photovoltaic System

Renewable energy has gained significant attention of researchers in the last years, mainly due to the importance of using unlimited energy sources to supply homes, industries, cities and countries. In this context, this document focuses on the solar injection by employing a neutral point clamped (NPC) topology together with utilization of a maximum power point tracking (MPPT) and space vector modulation (SVM) techniques. Model predictive control (MPC) is employed to manage the currents and track their references. The proposed algorithms do not employ a cost function to decide which voltage to apply resulting in a spread frequency spectrum, and instead, a concentrated SVM spectrum is imposed. Notwithstanding, the DC link capacitors voltage balance is ensured and the computational burden is notably reduced as compared to traditional Finite Set Model Predictive Control (FS-MPC). Nevertheless, the consistent results are a consequence of the critical analysis that shows the feasibility of the proposal and guarantees the good performance of the entire system in simulated and experimental platforms.

Unified SVPWM Algorithm and Optimization for Single-Phase Three-Level NPC Converters

The high-order harmonics caused by the modulation strategy can deteriorate power quality. The harmonic characteristics of the carrier-based pulsewidth modulation are relatively fixed and difficult to optimize, while space vector pulsewidth modulation (SVPWM) has more flexibility. The unified SVPWM design method for single-phase three-level neutral-point clamped (NPC) converters is fully presented in this article. Based on the proposed unified SVPWM method, two existing traditional vector sequences are designed first, and then several advanced multisegment SVPWM algorithms are proposed. According to the particularity of the three-level NPC topology, two hybrid SVPWM algorithms are proposed to optimize harmonic performance. Moreover, the high-order harmonic characteristics and the number of switching actions are analyzed in detail for all SVPWM algorithm modes. In addition, these SVPWM algorithms are associated and unified by introducing weight coefficients of the redundant vectors. Simulation and experimental results verify the feasibility and effectiveness of the proposed SVPWM algorithms, which show that the proposed methods can optimize high-order harmonic distribution and reduce the line current harmonics.