Clamping Modulation Scheme for Low-Speed Operation of Three-Level Inverter Fed Induction Motor Drive With Reduced CMV

Abstract

This article introduces a family of carrier-based pulse width modulation (PWM) schemes for three-level (3 L) inverter fed motor drive for low-speed operation. The proposed PWM in dual-inverter topology (DIT) simultaneously clamps two phases of each inverter throughout the fundamental cycle, which reduces the switching transition in the pole voltage and common-mode voltage (CMV). Four PWM variants in the family (i.e., PWM-1–PWM-4) are discussed and compared with conventional discontinuous PWM schemes. A mapping of the gating pulse is derived to extend the proposed PWM to a classical 3 L inverter fed star-connected motor drive. The gating pulses are generated using triangular carrier comparison with synchronous sampling. The steady-state and dynamic performances of PWM are validated both in DIT fed open-end winding induction motor (IM) drive and neutral point clamped (NPC) inverter fed star-connected IM drive. It is observed that the proposed PWM gives inherent capacitor voltage balance in the NPC topology. PWM-1 has a higher linear modulation range than conventional zero clamp PWM and leads to reduced CMV in the NPC topology. PWM-2 and PWM-3 give reduced CMV in DIT. PWM-4 has fault tolerance to single-phase open-switch and short-switch failure in DIT.